Invention Grant
US09123418B2 NAND flash memory unit and NAND flash memory array 有权
NAND闪存单元和NAND闪存阵列

NAND flash memory unit and NAND flash memory array
Abstract:
A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.
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