公开(公告)号：US20140239380A1

公开(公告)日：2014-08-28

申请号：US14269212

申请日：2014-05-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Riichiro Shirota ,  Nina Mitiukhina ,  Tsai-Hao Kuo

IPC: H01L27/115

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11578

Abstract: A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.

Abstract translation: 描述了NAND​​闪存单元，其包括串联连接的一串存储器单元，耦合到串的两个端子的S / D区，串的端子与S / D区之间的至少一个选择晶体管耦合，以及 所述至少一个擦除晶体管耦合在所述至少一个选择晶体管和S / D区之间。 选择晶体管用于选择存储单元串。 擦除晶体管用于减小选择晶体管的Vt-偏移。

公开(公告)号：US11809706B2

公开(公告)日：2023-11-07

申请号：US17349918

申请日：2021-06-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Yu-Cheng Hsu ,  Tsai-Hao Kuo ,  Wei Lin ,  An-Cheng Liu

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.

公开(公告)号：US20200035306A1

公开(公告)日：2020-01-30

申请号：US16120313

申请日：2018-09-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Tsai-Hao Kuo ,  Szu-Wei Chen ,  Lih Yuarn Ou ,  Hsiao-Yi Lin

IPC: G11C16/26 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C16/04

Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.

公开(公告)号：US09123418B2

公开(公告)日：2015-09-01

申请号：US14269212

申请日：2014-05-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Riichiro Shirota ,  Nina Mitiukhina ,  Tsai-Hao Kuo

IPC: G11C16/10 ,  G11C16/04 ,  H01L27/115 ,  G11C16/14

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11578

Abstract: A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.

Abstract translation: 描述了NAND​​闪存单元，其包括串联连接的一串存储器单元，耦合到串的两个端子的S / D区，串的端子与S / D区之间的至少一个选择晶体管耦合，以及 所述至少一个擦除晶体管耦合在所述至少一个选择晶体管和S / D区之间。 选择晶体管用于选择存储单元串。 擦除晶体管用于减小选择晶体管的Vt-偏移。

公开(公告)号：US20220342547A1

公开(公告)日：2022-10-27

申请号：US17349918

申请日：2021-06-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Yu-Cheng Hsu ,  Tsai-Hao Kuo ,  Wei Lin ,  An-Cheng Liu

IPC: G06F3/06

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.

公开(公告)号：US10679707B2

公开(公告)日：2020-06-09

申请号：US16120313

申请日：2018-09-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Tsai-Hao Kuo ,  Szu-Wei Chen ,  Lih Yuarn Ou ,  Hsiao-Yi Lin

IPC: G06F3/01 ,  G11C16/26 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C16/04 ,  G11C11/56

Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.