公开(公告)号：US20140239380A1

公开(公告)日：2014-08-28

申请号：US14269212

申请日：2014-05-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Riichiro Shirota ,  Nina Mitiukhina ,  Tsai-Hao Kuo

IPC: H01L27/115

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11578

Abstract: A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.

Abstract translation: 描述了NAND​​闪存单元，其包括串联连接的一串存储器单元，耦合到串的两个端子的S / D区，串的端子与S / D区之间的至少一个选择晶体管耦合，以及 所述至少一个擦除晶体管耦合在所述至少一个选择晶体管和S / D区之间。 选择晶体管用于选择存储单元串。 擦除晶体管用于减小选择晶体管的Vt-偏移。

公开(公告)号：US09123418B2

公开(公告)日：2015-09-01

申请号：US14269212

申请日：2014-05-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Riichiro Shirota ,  Nina Mitiukhina ,  Tsai-Hao Kuo

IPC: G11C16/10 ,  G11C16/04 ,  H01L27/115 ,  G11C16/14

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11578

Abstract: A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.

Abstract translation: 描述了NAND​​闪存单元，其包括串联连接的一串存储器单元，耦合到串的两个端子的S / D区，串的端子与S / D区之间的至少一个选择晶体管耦合，以及 所述至少一个擦除晶体管耦合在所述至少一个选择晶体管和S / D区之间。 选择晶体管用于选择存储单元串。 擦除晶体管用于减小选择晶体管的Vt-偏移。

公开(公告)号：US20140050024A1

公开(公告)日：2014-02-20

申请号：US13781718

申请日：2013-02-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Riichiro Shirota ,  Wei Lin

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483

Abstract: A data reading method for a rewritable non-volatile memory module, a memory controller using the method, and a memory storage apparatus using the method are provided. The method includes applying a bias for reading data to a target word line electrically connected to a target memory cell and applying a bias for selecting bit lines to a target bit line electrically connected to the target memory cell. The method also includes applying a first bias to at least one word line adjacent to the target word line and applying a second bias to other word lines, and the first bias is lower than the second bias. The method further includes outputting a corresponding value according to a conduction state of a channel of the target memory cell. Accordingly, the method can effectively increase the gate controllability of the memory cell to prevent read errors.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的数据读取方法，使用该方法的存储器控​​制器和使用该方法的存储器存储装置。 所述方法包括：向与目标存储单元电连接的目标字线上应用读取数据的偏置，并向与目标存储单元电连接的目标位线施加用于选择位线的偏置。 该方法还包括将第一偏压施加到与目标字线相邻的至少一个字线，并将第二偏压施加到其它字线，并且第一偏压低于第二偏压。 该方法还包括根据目标存储器单元的通道的导通状态输出相应的值。 因此，该方法可以有效地提高存储单元的门控制性，以防止读错误。