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    Simultaneous detection and data transmission
    1.
    发明专利
    Simultaneous detection and data transmission 有权
    同时检测和数据传输

    公开(公告)号：JP2008278456A

    公开(公告)日：2008-11-13

    申请号：JP2008002202

    申请日：2008-01-09

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc

    Inventor： HU WENDONG

    IPC: H04W16/14 ,  H04W72/08

    CPC classification number: H04W72/085 ,  H04W16/14 ,  H04W72/082

    Abstract: PROBLEM TO BE SOLVED: To provide a system having the minimum interference, which increases the transmission capacity by minimizing interruption and transmission delay.
    SOLUTION: The present system for use by a wireless regional area network (WRAN) is provided with a WRAN cell to be operated by a BS for wireless communication with at least one consumer terminal, determines an available channel by operating the BS, provides an in-band channel for data transmission by initializing the channel, and concurrently executes spectrum management for a plurality of out-band channels, spectrum detection, and data transmission for the in-band channel.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供具有最小干扰的系统，其通过最小化中断和传输延迟来增加传输容量。 解决方案：由无线区域网（WRAN）使用的本系统提供有由BS操作的WRAN小区，用于与至少一个消费者终端进行无线通信，通过操作BS来确定可用信道， 通过初始化通道提供用于数据传输的带内信道，并且同时执行用于带内信道的多个带外信道的频谱管理，频谱检测和数据传输。 版权所有（C）2009，JPO＆INPIT

    Random access memory array with parity bit structure
    2.
    发明专利
    Random access memory array with parity bit structure 审中-公开
    随机访问存储器阵列与奇偶位结构

    公开(公告)号：JP2006019005A

    公开(公告)日：2006-01-19

    申请号：JP2005189664

    申请日：2005-06-29

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc

    Inventor： FREY CHRISTOPHE

    IPC: G11C11/15

    CPC classification number: G06F11/1076 ,  G11C7/1006 ,  G11C11/16 ,  G11C16/10 ,  G11C2211/5646 ,  G11C2211/5647

    Abstract: PROBLEM TO BE SOLVED: To improve a random access memory array about array structure supporting necessity of a decreased write-in current for a memory array. SOLUTION: A random access memory array includes first random access memory elements arranged in a plurality of rows and columns for storing data words at a multiple memory locations. The memory array further includes second random access memory elements arranged in at least one additional column. Each second random access memory element is associated with a memory location to store a flag value indicative of whether the data word stored at that memory location is a true or complement version. The individual memory elements may comprise magnetic random access memory elements. Alternatively, the individual memory elements may comprise flash memory cells. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：改进关于阵列结构的随机存取存储器阵列，其支持对存储器阵列的减小的写入电流的必要性。 解决方案：随机存取存储器阵列包括以多个行和列排列的用于在多个存储器位置存储数据字的第一随机存取存储器元件。 存储器阵列还包括布置在至少一个附加列中的第二随机存取存储器元件。 每个第二随机存取存储器元件与存储器位置相关联，以存储指示存储在该存储器位置的数据字是真还是补补版本的标志值。 各个存储元件可以包括磁性随机存取存储器元件。 或者，各个存储元件可以包括闪存单元。 版权所有（C）2006，JPO＆NCIPI

    Disk drive write driver with boosting circuit to improve output voltage swing
    3.
    发明专利
    Disk drive write driver with boosting circuit to improve output voltage swing 审中-公开
    带升压电路的磁盘驱动器驱动器，以提高输出电压摆幅

    公开(公告)号：JP2005327452A

    公开(公告)日：2005-11-24

    申请号：JP2005139508

    申请日：2005-05-12

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc

    Inventor： ALINI ROBERTO ,  POSAT BARIS ,  VENCA ALESANDRO

    IPC: G11B5/09 ,  G05F3/26 ,  G11B5/00 ,  G11B5/02 ,  H02M3/07

    CPC classification number: G11B5/09 ,  G11B2005/0016 ,  H02M3/073

    Abstract: PROBLEM TO BE SOLVED: To provide an improved circuit and method for driving a write head in a hard disk drive (HDD) system.
    SOLUTION: The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit is connected between a high voltage reference or supply voltage and a low voltage reference, and includes a current source, such as a MOS transistor, connected to the input node of a capacitor. During the overshoot duration, the current source operates at saturation to generate a pulsed current with an amplitude of half the load current. The circuit includes another transistor in series with the current generator between the capacitor and the driver output. A forward bias diode is connected between the capacitor output node and high voltage reference and enters reverse bias during overshoot duration swinging the driver output voltage above supply voltage.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供用于驱动硬盘驱动器（HDD）系统中的写入头的改进的电路和方法。 解决方案：写入驱动器包括匹配输出电阻到互连的奇特性阻抗的电路和升压电路。 升压电路连接在高电压基准或电源电压和低电压基准之间，并且包括连接到电容器的输入节点的诸如MOS晶体管的电流源。 在过冲持续时间期间，电流源工作在饱和状态以产生具有一半负载电流幅度的脉冲电流。 电路包括与电容器和驱动器输出之间的电流发生器串联的另一个晶体管。 正向偏置二极管连接在电容器输出节点和高电压基准之间，并在驱动器输出电压高于电源电压的过冲持续时间期间进入反向偏置。 版权所有（C）2006，JPO＆NCIPI

    Read head preamplifier with thermal asperity transient control
    4.
    发明专利
    Read head preamplifier with thermal asperity transient control 审中-公开
    阅读具有热平衡瞬态控制的头部前置放大器

    公开(公告)号：JP2005293829A

    公开(公告)日：2005-10-20

    申请号：JP2005099165

    申请日：2005-03-30

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc

    Inventor： POSAT BARIS ,  ALINI ROBERTO ,  OZANOGLU KEMAL

    IPC: G11B5/09 ,  G11B5/00 ,  G11B20/10 ,  G11B20/22

    CPC classification number: G11B20/10009 ,  G11B20/22 ,  G11B2005/0016

    Abstract: PROBLEM TO BE SOLVED: To correct for thermal asperity transients occurring in a hard disk drive.
    SOLUTION: The preamplifier 110 has an input gain stage receiving a signal from an MR head 128, a thermal asperity transient correcting circuit 111, and an output buffer outputting a reader output to a read channel. The thermal asperity transient correcting circuit 111 is composed of a high-pass filter and voltage controlled based upon an input control signal from a filter controller. The filter controller uses a low-pass filter functioning as a peak detector to detect peaks in either the input or output voltage of the high-pass filter. The low pass filter output is applied to a non-linear function generator generating the control signal for the high pass filter based on an increasing function of the absolute value of the low pass filter output.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：纠正在硬盘驱动器中出现的热凹凸瞬变。 解决方案：前置放大器110具有接收来自MR头128的信号的输入增益级，热凹凸瞬变校正电路111和将读取器输出输出到读通道的输出缓冲器。 热绝缘瞬态校正电路111由高通滤波器和基于来自滤波器控制器的输入控制信号进行电压控制而组成。 滤波器控制器使用用作峰值检测器的低通滤波器来检测高通滤波器的输入或输出电压中的峰值。 低通滤波器输出被应用于基于低通滤波器输出的绝对值的增加函数产生高通滤波器的控制信号的非线性函数发生器。 版权所有（C）2006，JPO＆NCIPI

    Method and apparatus0 for usb and non-contact smart card device
    6.
    发明专利
    Method and apparatus0 for usb and non-contact smart card device 审中-公开
    USB和非接触式智能卡设备的方法和设备

    公开(公告)号：JP2005078651A

    公开(公告)日：2005-03-24

    申请号：JP2004256462

    申请日：2004-09-03

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

    Inventor： FRUHAUF SERGE

    IPC: G06K19/07 ,  G06K19/077

    CPC classification number: G06K19/07739 ,  G06K19/077 ,  G06K19/07733 ,  G06K19/07769

    Abstract: PROBLEM TO BE SOLVED: To provide method and apparatus for a smart card device supporting both wireless and wired modes. SOLUTION: The apparatus is provided for a universal serial bus (USB) and wireless smart card device. The apparatus includes a mode detector, switching block, controller, antenna and wired interface. Further, an apparatus for a triple mode smart card is provided. The apparatus for the triple mode smart card includes the mode detector, switching block, controller, antenna and wired interface. The apparatus operates in one mode out of wireless, USB and International Standard Organization 7816 mode or other wired modes. Further, the apparatus for either one of these smart cards can operate in both wireless and wired modes without conflict and on and off of a power switch to change configuration. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供支持无线和有线模式的智能卡设备的方法和装置。

    解决方案：该设备用于通用串行总线（USB）和无线智能卡设备。 该装置包括模式检测器，开关块，控制器，天线和有线接口。 此外，提供了一种用于三模式智能卡的装置。 三模智能卡的装置包括模式检测器，开关块，控制器，天线和有线接口。 该设备以无线，USB和国际标准组织7816模式或其他有线模式的一种模式运行。 此外，这些智能卡中的任何一个的装置可以在无冲突的情​​况下以无线和有线模式工作，并且能够切换电力开关以改变配置。 版权所有（C）2005，JPO＆NCIPI

    Integrated data jitter generator for high-speed serial interface testing
    8.
    发明专利
    Integrated data jitter generator for high-speed serial interface testing 审中-公开

    公开(公告)号：JP2004336800A

    公开(公告)日：2004-11-25

    申请号：JP2004140051

    申请日：2004-05-10

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

    Inventor： HILL JOHN P

    IPC: G06F13/00 ,  G01R31/317 ,  H03K5/156 ,  H04L1/20 ,  H04L27/12

    CPC classification number: G01R31/31709 ,  G01R31/31715 ,  H04L1/205

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a unit offering a high-speed jitter testing capability.
    SOLUTION: The prevention provides an integrated data generator for testing a high-speed serial interface. A transmission timing generator used in a transmit data path includes a high-frequency clock generator such as a phase lock loop and a delay lock loop or the like equipped with an input for receiving an oscillator or a base clock input. A clock modulator receives both of existing low-frequency and high-frequency modulating signals. A high-speed modulating clock signal is generated to allow a jitter testing to be conducted with a receiver combined with downstream. Although a fixed frequency such as 3, 6, 125, 150, 250, 300, 750, 1,500 MHz or the like is used for the high-speed modulating signal for example, any high-speed modulating frequency can be used for generating an intended volume of jitter. In a similar way, the amplitude of the high-frequency modulating signal can be varied as desired.
    COPYRIGHT: (C)2005,JPO&NCIPI

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