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公开(公告)号：KR101374322B1
公开(公告)日：2014-03-17
申请号：KR1020100125025
申请日：2010-12-08
Applicant: 한국전자통신연구원
IPC: H01L21/336 , H01L29/78
Abstract: 반도체 소자의 제조 방법이 제공된다. 반도체 소자의 제조 방법은 제1 도전형의 반도체 기판에 트렌치를 형성하는 것, 트렌치의 측벽 및 바닥면 상에 제2 도전형의 도펀트를 포함하는 트렌치 도펀트 함유막을 형성하는 것, 트렌치 도펀트 함유막 내의 도펀트를 반도체 기판으로 확산시키는 것, 및 트렌치 도펀트 함유막을 제거하는 것을 포함한다.
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公开(公告)号：KR1020140092209A
公开(公告)日：2014-07-23
申请号：KR1020130129431
申请日：2013-10-29
Applicant: 한국전자통신연구원
IPC: H01L29/08
Abstract: The present invention provides a structure of a semiconductor power rectifying device. The structure of the semiconductor power rectifying device includes a first conductivity type doped substrate; a second electrode which is provided on the lower surface of the substrate; an active region and a field region which are defined on the substrate; a gate which is provided on the active region; a gate insulating layer which is provided between the gate and the substrate; body regions which are provided in the substrate adjacent to the first and second sides of the gate which face each other and are doped with the dopant of a second conductivity type which is different from the first conductivity type; and a plug region of a second conductivity type which is formed in the substrate adjacent to the third and the forth sides of the gate which connect the first and the second sides.
Abstract translation: 本发明提供一种半导体功率整流装置的结构。 半导体功率整流装置的结构包括第一导电型掺杂衬底; 设置在基板的下表面上的第二电极; 限定在所述基板上的有源区域和场区域; 设置在有源区上的栅极; 栅极绝缘层，其设置在所述栅极和所述基板之间; 本体区域设置在与栅极的第一和第二侧相邻的衬底中，所述第一和第二侧彼此面对并且掺杂有与第一导电类型不同的第二导电类型的掺杂物; 以及第二导电类型的插塞区域，其形成在与栅极的连接第一和第二侧面的第三和第四侧相邻的基板中。
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公开(公告)号：KR1020130081547A
公开(公告)日：2013-07-17
申请号：KR1020120002583
申请日：2012-01-09
Applicant: 한국전자통신연구원
Inventor： 나경일
CPC classification number: H01L21/84 , H01L27/1203
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof provide a smart power integrated circuit with trench double diffused metal-oxide-semiconductor (TDMOS) power device, thereby improving current driving capacity. CONSTITUTION: An insulating layer is interposed between a lower plate (10) and an upper plate (20). An isolation pattern isolates a first device and a second device. A doping pattern is interposed between the upper plate and the insulating layer; the upper plate and an epi layer (14). The first device is electrically connected with the lower plate through the doping pattern and epi layer. The second device is electrically isolated from the lower plate through the doping pattern and insulating layer.
Abstract translation: 目的：一种半导体器件及其制造方法，提供具有沟槽双扩散金属氧化物半导体（TDMOS）功率器件的智能功率集成电路，从而提高电流驱动能力。 构成：在下板（10）和上板（20）之间插入绝缘层。 隔离模式隔离第一设备和第二设备。 在上板和绝缘层之间插入掺杂图案; 上板和外延层（14）。 第一器件通过掺杂图案和外延层与下板电连接。 第二器件通过掺杂图案和绝缘层与下板电隔离。
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公开(公告)号：KR101790520B1
公开(公告)日：2017-10-27
申请号：KR1020120053276
申请日：2012-05-18
Applicant: 한국전자통신연구원
Inventor： 나경일
IPC: H01L21/337 , H01L29/808
CPC classification number: H01L29/66825 , H01L21/2254 , H01L21/2255 , H01L29/0634 , H01L29/407 , H01L29/66734 , H01L29/7813
Abstract: 본발명의실시예에따른반도체소자제조방법은제 1 도전형의반도체기판을식각하여제 1 트렌치를형성하는것, 상기제 1 트렌치로부터연장하는제 2 트렌치를형성하는것, 상기제 2 트렌치내벽으로불순물을확산하여상기제 2 트렌치를감싸는제 2 도전형의불순물영역을형성하는것, 상기제 2 트렌치내벽을덮는플로팅절연막과상기제 2 트렌치를채우는플로팅전극을형성하는것, 및상기제 1 트렌치내벽을덮는게이트절연막과상기제 1 트렌치를채우는게이트전극을형성하는것을포함할수 있다.
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公开(公告)号：KR101736282B1
公开(公告)日：2017-05-16
申请号：KR1020110122088
申请日：2011-11-22
Applicant: 한국전자통신연구원
IPC: H01L29/78 , H01L21/336 , H01L21/28
Abstract: 반도체소자가제공된다. 본발명에따른반도체소자는반도체기판내에배치되는필라부, 상기반도체기판내에상기필라부와이격되는필드플레이트전극, 상기반도체기판내에상기필드플레이트전극상에배치되는게이트패턴, 상기필드플레이트전극은상기게이트패턴의하단과연결되는것, 상기반도체기판과상기필드플레이트전극사이에배치되는필드플레이트유전막및 상기반도체기판과상기게이트패턴의측벽사이에배치되고, 상기필드플레이트유전막보다얇은두께를갖는게이트유전패턴을포함할수 있다.
Abstract translation: 提供了一种半导体器件。 根据本发明，柱部，栅极图案，以及设置在所述半导体衬底中的场板电极的半导体装置，所述半导体衬底，所述柱部和该间隔的电极场板，在上半导体衬底提供的场板电极是 doeneungeot连接到栅极图案的下端，设置在所述半导体基板和所述场之间，所述场板电介质层和所述半导体衬底的侧壁和栅极图案被设置在电极板之间，具有厚度比所述场板电介质层更薄的栅极介电图案 在可以包含。
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Patent Agency Ranking
公开(公告)号：KR1020130056464A
公开(公告)日：2013-05-30
申请号：KR1020110122088
申请日：2011-11-22
Applicant: 한국전자통신연구원
IPC: H01L29/78 , H01L21/336 , H01L21/28
CPC classification number: H01L29/402 , H01L21/28211 , H01L21/28229 , H01L21/28264 , H01L29/4232 , H01L29/66712
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to increase a breakdown voltage by distributing an electric field due to a high voltage through a field plate electrode. CONSTITUTION: A pillar part(160a) is arranged on a semiconductor substrate(100). A field plate electrode(145b) is separated from the pillar part. A gate pattern(145a) is arranged on the field plate electrode which is located on the semiconductor substrate. A field plate dielectric layer(120) is arranged between the semiconductor substrate and the field plate electrode. A gate dielectric pattern(135) is arranged between the semiconductor substrate and the sidewall of the gate pattern.
Abstract translation: 目的：提供一种半导体器件及其制造方法，以通过通过场板电极分配由高电压引起的电场来增加击穿电压。 构成：在半导体基板（100）上配置有支柱部（160a）。 场板电极（145b）与柱部分离。 栅极图案（145a）布置在位于半导体衬底上的场板电极上。 在半导体衬底和场板电极之间设置场板电介质层（120）。 栅极电介质图案（135）布置在半导体衬底和栅极图案的侧壁之间。
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公开(公告)号：KR1020120061708A
公开(公告)日：2012-06-13
申请号：KR1020100125025
申请日：2010-12-08
Applicant: 한국전자통신연구원
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/7801 , H01L29/66674
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to manufacture the semiconductor device with high reliability by forming uniform density of a second conductivity type dopant within a doping region. CONSTITUTION: A trench(121) is formed on a first conductivity type semiconductor substrate. A trench dopant containing film(130) which includes a second conductivity type dopant is formed on the bottom surface and a side wall of the trench. A doping region(132) is formed by diffusing the dopant within the trench dopant containing film to the inside the semiconductor substrate. The trench dopant containing film is eliminated.
Abstract translation: 目的：提供一种半导体器件及其制造方法，以通过在掺杂区域内形成均匀的第二导电型掺杂剂的密度来制造具有高可靠性的半导体器件。 构成：在第一导电型半导体衬底上形成沟槽（121）。 在沟槽的底表面和侧壁上形成包括第二导电型掺杂剂的含沟槽掺杂剂的膜（130）。 掺杂区域（132）通过将沟槽掺杂剂膜内的掺杂剂扩散到半导体衬底的内部而形成。 消除了含沟槽掺杂剂的膜。
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公开(公告)号：KR1020140035787A
公开(公告)日：2014-03-24
申请号：KR1020130002510
申请日：2013-01-09
Applicant: 한국전자통신연구원
IPC: H01L29/86 , H01L29/8605 , H01L29/872
Abstract: According to a power rectifying device in the embodiments of the present invention, a gate electrode, a source region and a body region are commonly connected to a first terminal. A substrate beside the body region is connected to a second terminal. Thereby, a power rectifying device having two terminals is realized. The gate electrode may have a spacer shape. Thereby, the channel depth of the channel region of the trench structure of the power rectifying device can be accurately controlled by controlling the width of the gate electrode.
Abstract translation: 根据本发明的实施方式的功率整流装置，栅电极，源极区域和主体区域共同地连接到第一端子。 身体区域旁边的基板连接到第二端子。 由此，实现具有两个端子的电力整流装置。 栅电极可以具有间隔件形状。 由此，可以通过控制栅电极的宽度来精确地控制功率整流装置的沟槽结构的沟道区域的沟道深度。
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公开(公告)号：KR1020130128996A
公开(公告)日：2013-11-27
申请号：KR1020120053276
申请日：2012-05-18
Applicant: 한국전자통신연구원
Inventor： 나경일
IPC: H01L21/337 , H01L29/808
CPC classification number: H01L29/66825 , H01L21/2254 , H01L21/2255 , H01L29/0634 , H01L29/407 , H01L29/66734 , H01L29/7813
Abstract: A method for manufacturing a semiconductor device according to the embodiment comprises; a step which forms a first trench by etching a semiconductor substrate of a first conductive type; a step which forms a second trench extended from the first trench; a step which forms a foreign matter area of a second conductive type surrounding the second trench by defusing a foreign matter to an inner wall of the second trench; a step which forms a floating insulating film covering the inner wall of the second trench and a floating electrode filling the second trench; a step which forms a gate insulating film covering an inner wall of the first trench and a gate electrode filling the first trench.
Abstract translation: 根据实施例的半导体器件的制造方法包括： 通过蚀刻第一导电类型的半导体衬底形成第一沟槽的步骤; 形成从所述第一沟槽延伸的第二沟槽的步骤; 通过将异物排除到第二沟槽的内壁来形成围绕第二沟槽的第二导电类型的异物区域的步骤; 形成覆盖所述第二沟槽的内壁的浮动绝缘膜和填充所述第二沟槽的浮动电极的步骤; 形成覆盖第一沟槽的内壁的栅极绝缘膜和填充第一沟槽的栅电极的步骤。
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公开(公告)号：KR1020150010472A
公开(公告)日：2015-01-28
申请号：KR1020130085554
申请日：2013-07-19
Applicant: 한국전자통신연구원
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/4238 , H01L29/7802 , H01L29/7811
Abstract: 본 발명은 전력 정류 소자를 개시한다. 그의 소자는, 기판과, 상기 기판 상의 소스 층과, 상기 소스 층 상의 채널 층과, 상기 채널 층 상에 개별적으로 분리된 게이트 패턴들과, 상기 게이트 패턴들과 상기 채널 층 사이의 게이트 절연막들과, 상기 게이트 패턴들 사이의 상기 채널 층 내에 형성된 드레인을 포함한다. 상기 게이트 패턴들은, 상기 기판의 셀(Cell) 영역 상에서 넓은 선폭(wide width)과 좁은 선폭(short width)이 조합된 십자 모양, 티자 모양, 원형 모양, 직사각형 모양, 팔각형 모양 중 어느 하나의 모양으로 배치되고, 상기 기판 가장자리(Peripheral) 영역을 둘러싸는 링 모양으로 배치될 수 있다.
Abstract translation: 本发明公开了一种电力整流装置。 根据本发明的电力整流装置包括衬底，衬底上的源极层，源极层上的沟道层，形成在沟道层上并彼此分离的栅极图案，插入在栅极图案之间的栅极绝缘层和 沟道层，以及沟槽层中形成的漏极，插入在栅极图案之间。 栅极图案可以以通过组合具有宽线宽度的线和窄线宽窄线形成的交叉形状之一形成在基板的单元区域上，T形，圆形， 矩形形状和八边形，并且可以设置成围绕基板的周围区域以环形形状。
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