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公开(公告)号：KR100170190B1
公开(公告)日：1999-03-30
申请号：KR1019950047061
申请日：1995-12-06
Applicant: 한국전자통신연구원
IPC: H04W36/38
Abstract: 본 발명은 CDMA 이동통신시스템에서 트래픽 부하 제어방법에 관한 것이다.
CDMA의 디지탈 이동통신시스템에서 특정 셀 영역에 트래픽 부하가 증가하여 자기가 처리할 수 있는 용량을 초과할 경우 순방향 링크의 커버리지를 줄이지 않고 기지국이 관리하는 전력의 할당상태에 기초하여 특정 셀의 가장자리에서 통화중인 이동가입자들을 트래픽 밀도가 보다 낮은 인접 셀 영역으로 소프트 핸드오프를 유도함으로써 과도한 트래픽 부하를 효과적으로 제어하기 위한 것이다.-
公开(公告)号：KR1019950005146B1
公开(公告)日：1995-05-18
申请号：KR1019910022630
申请日：1991-12-11
Applicant: 한국전자통신연구원
IPC: H04L12/42
Abstract: The information switching circuit of a token bus controller enables the controller to transmit and receive data to/from coaxial cable through modem. The circuit comprises a token bus controller to trasmit and receive data between modem and 80186 processor; an interface conversion circuit to convert timing of transmitting or receiving data bit stream; and DRAM controller to control data read and write from/to DRAM. The circuit provides easy interface with minimap.
Abstract translation: 令牌总线控制器的信息切换电路使得控制器能够通过调制解调器向/从同轴电缆接收数据。 该电路包括令牌总线控制器，用于在调制解调器和80186处理器之间传输和接收数据; 用于转换发送或接收数据比特流的定时的接口转换电路; 和DRAM控制器，用于控制从DRAM到DRAM的数据读写。 该电路提供了与小地图的简单接口。
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公开(公告)号：KR1019950001232B1
公开(公告)日：1995-02-15
申请号：KR1019910022632
申请日：1991-12-11
Applicant: 한국전자통신연구원
IPC: G06F13/14
Abstract: The bus arbitration circuit enables a processor and a token-bus controller to access the shared memory region without polling and interrupt in order to remove data-conflict. The MAP network controller comprises a processor, a token-bus controller, a shared memory region, a bus arbitration circuit. The bus arbitration circiut comprises the first D flip-flop inputting bus request from the token-bus controller and outputting bus hold signal; the second D flip-flop inputting bus hold acknowledge signal and outputting bus grant to the token-bus controller; AND gate arbitrating the bus access right.
Abstract translation: 总线仲裁电路使得处理器和令牌总线控制器能够访问共享存储器区域而不进行轮询和中断，以便消除数据冲突。 MAP网络控制器包括处理器，令牌总线控制器，共享存储器区域，总线仲裁电路。 总线仲裁循环包括来自令牌总线控制器的第一个D触发器输入总线请求并输出总线保持信号; 第二D触发器输入总线保持确认信号并将总线授权输出到令牌总线控制器; 和门仲裁总线访问权限。
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Patent Agency Ranking
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公开(公告)号：KR1019930007081B1
公开(公告)日：1993-07-29
申请号：KR1019900021823
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: The field bus interface board supports serial communication between host computer and peripheral equipments for process control. The interface board includes a first decoder (5) for decoding address signal transmitted from latches (2,2a) to generate chip selection signals, a PC interfacing unit (12) for interfacing a personal computer (PC) and dual ported RAM (4), a second decoder (13) for decoding control signals coming from a PC to generate chip selection signal of dual ported RAM (4), an encoder/decoder (9) for encoding input data to generate Manchester code and for decoding Manchester code, a first and a second latch/shift registers (7,8) for converting parallel data to serial data, a CRC generator (11) for checking data transmission error, and an interface unit (10) for interfacing the Manchester encoder/decoder (9) and field bus.
Abstract translation: 现场总线接口板支持主机与外围设备之间的串行通信，用于过程控制。 接口板包括用于解码从锁存器（2,2a）发送的地址信号以产生芯片选择信号的第一解码器（5），用于将个人计算机（PC）和双端口RAM（4）接口的PC接口单元（12） ，用于解码来自PC的控制信号以产生双端口RAM（4）的芯片选择信号的第二解码器（13），用于对输入数据进行编码以产生曼彻斯特码并用于解码曼彻斯特码的编码器/解码器（9）， 用于将并行数据转换为串行数据的第一和第二锁存/移位寄存器（7,8），用于检查数据传输错误的CRC发生器（11）以及用于将曼彻斯特编码器/解码器（9）接口的接口单元（10） 和现场总线。
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