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公开(公告)号：JPH10215266A
公开(公告)日：1998-08-11
申请号：JP36135497
申请日：1997-12-26
Applicant: COMPAQ COMPUTER CORP
Inventor： KOTZUR GARY B , MAYER DALE J , WITKOWSKI MICHAEL L , WALKER WILLIAM J , HARESKI PATRICIA E
Abstract: PROBLEM TO BE SOLVED: To make it easy to transfer data directly to another port in cut- through mode by providing network ports, a data bus, and a memory for data transfer, providing a switch manager which controls a data flow, and implementing a network switching function in store and forward mode and also providing individual cut-through buffers. SOLUTION: A network switch 102 is connected to a B network 112 by B ports 110 through a proper media segment 114 such as an optical fiber and performs data transfer in store and forward mode of 100MHz. Further, (J+1) A networks 106 are coupled with (j+1) ports 104 through a media segment 108. Computer systems or work stations 120, 122, and 124 which constitute the A network 106 communicate with each other or with other devices of other networks in cut-through mode through the network switch 102.
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公开(公告)号：JPH10243013A
公开(公告)日：1998-09-11
申请号：JP36120497
申请日：1997-12-26
Applicant: COMPAQ COMPUTER CORP
Inventor： WALKER WILLIAM J , KOTZUR GARY B , HARESKI PATRICIA E , WITKOWSKI MICHAEL L , MAYER DALE J
Abstract: PROBLEM TO BE SOLVED: To provide the system that executes the simultaneous read write cycle in a network switch. SOLUTION: A network switch 102 includes some network ports, a data bus and a switch manager that execute the simultaneous read write cycle on the data bus by asserting a 1st port number to identify a source port followed by a 1st port number in order to identify a destination port. Data are directly transferred between the source port and the destination port without being buffered in the switch manager. Since the data are transferred only once through the data bus, the band width of the data bus is extended.
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公开(公告)号：DE69731936D1
公开(公告)日：2005-01-20
申请号：DE69731936
申请日：1997-12-30
Applicant: COMPAQ COMPUTER CORP
Inventor： WALKER WILLIAM J , KOTZUR GARY B , HARESKI PATRICIA E , MAYER DALE J , WITKOWSKI MICHAEL L
Abstract: A network switch including one or more network ports for receiving and transmitting data, where each port includes a network interface, a data bus interface and a processor port interface. a data bus coupled to the data bus interface of each of the ports, a processor bus coupled to a processor and to the processor port interface of each of the ports, and a memory bus coupled to a memory. The network switch further includes a switch manager coupled to the data bus, the processor bus and the memory bus for controlling data flow between the ports and said memory and for enabling the processor access to the ports and the memory. In this manner, the processor has direct and relatively independent access to the network ports for performing overhead functions, such as monitoring, determining status and configuration without consuming valuable bandwidth of the data bus.
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公开(公告)号：AU5351594A
公开(公告)日：1994-04-26
申请号：AU5351594
申请日：1993-09-30
Applicant: COMPAQ COMPUTER CORP
Inventor： MAYER DALE J , LANDRY JOHN A , CULLEY PAUL R
IPC: G06F13/24
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公开(公告)号：CA2028552A1
公开(公告)日：1991-05-04
申请号：CA2028552
申请日：1990-10-25
Applicant: COMPAQ COMPUTER CORP
Inventor： MAYER DALE J , CULLEY PAUL R , GOODRUM ALAN L
Abstract: BUS CLOCK EXTENDING MEMORY CONTROLLER A memory controller provides a stretch signal to a bus controller which develops the synchronizing signal used on a synchronized bus, alleviating the need to insert a full wait state during memory read operations. The memory is located off a second bus which is tightly coupled to the processor, but devices operating according to the protocol of the synchronized bus can access the memory. The memory controller controls the buffers and address multiplexing between the second bus and the memory devices, while the bus controller controls the buffering and latching between the first and second buses. The memory controller also develops the row and column address strobes used by the memory devices.
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Patent Agency Ranking
公开(公告)号：JPH11168494A
公开(公告)日：1999-06-22
申请号：JP26995898
申请日：1998-09-24
Applicant: COMPAQ COMPUTER CORP
Inventor： WITKOWSKI MICHAEL L , MAYER DALE J , WALKER WILLIAM J , ROLLER KIRK D , HARESKI PATRICIA E , KOTZUR GARY B
Abstract: PROBLEM TO BE SOLVED: To enlarge available band width between two network communication devices without substantial change and without increasing the band width of an optionally given port by selecting a bonded port and transmitting a packet. SOLUTION: A network switch 102 includes a port control circuit connected to respective ports 104 in order to control traffic flows of the ports 104. The network switch 102 includes a port bonding circuit which is connected to the port control circuit or incorporated in it. In the same way, the network switch includes a port control circuit connected to respective ports 108 so as to control data traffic and a port bonding circuit which is connected to the port control circuit or incorporated in it. Then, the switch 102 selects one of the bond ports 140 and 142 in order to transmit a packet from a bond port switch 120.
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公开(公告)号：JPH1097490A
公开(公告)日：1998-04-14
申请号：JP22340197
申请日：1997-08-20
Applicant: COMPAQ COMPUTER CORP
Inventor： MAYER DALE J , OLARIG SOMPONG P , WHITEMAN WILLIAM F , HEINRICH DAVID F
IPC: G06F13/18 , G06F13/24 , G06F13/362
Abstract: PROBLEM TO BE SOLVED: To assure the distribution of balanced interruption to a processor whose current task priority is the lowest among >= four processors by giving bus ownership to one that is selected from bus agent of the request source. SOLUTION: When a designated distribution mode interruption is made, data are sent to a destination processor on four data lines of a programmable interruption controller bus 311. A central programmable interruption controller COPIC 312 sends a 'distributed interruption' command to entire agents, and each agent gives its current task priority level(CTPR). The COPIC 312 compares CTPR values, selects an agent that has the smallest CTPR value and distributes interruption to the agent. Thereby, it is secured that interruption is distributed to an agent that always has margin in a dynamic distribution mode.
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公开(公告)号：DE69731366T2
公开(公告)日：2006-02-02
申请号：DE69731366
申请日：1997-12-30
Applicant: COMPAQ COMPUTER CORP
Inventor： HARESKI PATRICIA E , WALKER WILLIAM J , KOTZUR GARY B , MAYER DALE J , WITKOWSKI MICHAEL L
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公开(公告)号：DE69732086T2
公开(公告)日：2005-06-09
申请号：DE69732086
申请日：1997-12-30
Applicant: COMPAQ COMPUTER CORP
Inventor： MAYER DALE J , RICHTER ROGER , WITKOWSKI MICHAEL L , KOTZUR GARY B , HARESKI PATRICIA E , WALKER WILLIAM J
Abstract: A network switch including a central memory that stores device identification information, port numbers, control information, and packet data received at the ports of the switch. The memory includes a packet section that stores packet data and a device identification section that stores identification entries, where each entry corresponds to a network device coupled to a port of the switch. The switch includes a switch manager to control data flow between the ports and the central memory. Each of the identification entries includes a unique network address to identify one of the network devices and a port number to identify one of the network ports. Each of the identification entries is located within the central memory at a hash address derived by hashing the unique network address. Hash logic receives and hashes each network address to determine a hash address, which is used to access the identification entries. The memory is organized into a chain structure to enable quick access of entries. The switch manager further includes a control memory for storing control registers, including a freepool control register for identifying a freepool chain of memory sectors, a receive control register for identifying a corresponding receive sector chain and a transmit control register for identifying a corresponding transmit packet chain for each of the ports.
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公开(公告)号：DE69731519D1
公开(公告)日：2004-12-16
申请号：DE69731519
申请日：1997-12-30
Applicant: COMPAQ COMPUTER CORP
Inventor： WALKER WILLIAM J , KOTZUR GARY B , WITKOWSKI MICHAEL L , HARESKI PATRICIA E , MAYER DALE J
Abstract: A multiport polling system for a network switch including a plurality of network ports, each including receive and transmit buffers. Each port includes port status logic for providing status signals indicative of whether a corresponding port has received data from a network device and whether a corresponding port has available space to receive data to transmit to a network device. The network switch further includes a switch manager for controlling data flow between the ports. The switch manager includes polling logic for periodically polling the port status logic of each port for receiving the status signals, and a memory for storing values indicative of the status signals for each port. In this manner, all of the ports are simultaneously polled in a singe query and the receive and transmit status of each port is maintained in the memory. This facilitates arbitration and control logic, which continuously reviews the memory to determine when to retrieve data from a source port and when to transmit data to one or more destination ports. The ports are preferably implemented with quad cascade devices for providing multiplexed status signals.
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