公开(公告)号：US12243935B2

公开(公告)日：2025-03-04

申请号：US18487114

申请日：2023-10-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Johnatan Avraham Kantarovsky ,  Mark David Levy ,  Ephrem Gebreselasie ,  Yves Ngu ,  Siva P. Adusumilli

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/43 ,  H01L29/49 ,  H01L29/66

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

公开(公告)号：US12119383B2

公开(公告)日：2024-10-15

申请号：US18174052

申请日：2023-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/49 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/401 ,  H01L21/76897 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/452 ,  H01L29/475 ,  H01L29/49 ,  H01L29/4983

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US12087764B2

公开(公告)日：2024-09-10

申请号：US17890446

申请日：2022-08-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L21/8258 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0605 ,  H01L21/8258 ,  H01L27/0623 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/2003

Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.

公开(公告)号：US11978661B2

公开(公告)日：2024-05-07

申请号：US17118697

申请日：2020-12-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Fuad H. Al-Amoody ,  Felix P. Anderson ,  Spencer H. Porter ,  Mark D. Levy ,  Siva P. Adusumilli

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76865 ,  H01L23/5226 ,  H01L29/41725 ,  H01L23/5283 ,  H01L23/53295

Abstract: Disclosed is a structure with ultralow-K (ULK) dielectric-gap wrapped contact(s). The structure includes an opening, which extends through a dielectric layer and is aligned above a device. A contact is within the opening and electrically connected to the device. Instead of the contact completely filling the opening, a ULK dielectric-gap (e.g., an air or gas-filled gap or a void) at least partially separates the contact from the sidewall(s) of the contact opening and further wraps laterally around the contact. Also disclosed is a method for forming the structure and, particularly, for forming a ULK dielectric-gap by etching back an exposed top end of an adhesive layer initially lining a contact opening to form a gap between the sidewall(s) of the opening and the contact and then capping the gap with an additional dielectric layer such that the gap is filled with air or gas or is under vacuum.

公开(公告)号：US20240125732A1

公开(公告)日：2024-04-18

申请号：US18047405

申请日：2022-10-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bartlomiej J. Pawlak ,  Mark D. Levy ,  Siva P. Adusumilli ,  Ramsey M. Hazbun

IPC: G01N27/414

CPC classification number: G01N27/414

Abstract: A structure includes a cavity in a semiconductor substrate; a field effect transistor positioned over the cavity; an opening in the semiconductor substrate extending to the cavity; and a layer of insulating material filling the opening and forming an insulating material window to the cavity.

公开(公告)号：US11923446B2

公开(公告)日：2024-03-05

申请号：US17503345

申请日：2021-10-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Johnatan Avraham Kantarovsky ,  Mark David Levy ,  Ephrem Gebreselasie ,  Yves Ngu ,  Siva P. Adusumilli

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/49 ,  H01L29/43

CPC classification number: H01L29/7781 ,  H01L29/407 ,  H01L29/435 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/66431

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

公开(公告)号：US11842940B2

公开(公告)日：2023-12-12

申请号：US17156634

申请日：2021-01-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ramsey Hazbun ,  Siva P. Adusumilli ,  Mark David Levy ,  Alvin Joseph

IPC: H01L23/367 ,  H01L21/48

CPC classification number: H01L23/367 ,  H01L21/4882

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a heat generating device arranged over a substrate. An interlayer dielectric (ILD) material may be arranged over the heat generating device and the substrate. A metallization layer may be arranged over the interlayer dielectric material. A thermal shunt structure may be arranged proximal the heat generating device, whereby an upper portion of the thermal shunt structure may be arranged in the interlayer dielectric material and may be lower than the metallization layer, and a lower portion of the thermal shunt structure may be arranged in the substrate.

公开(公告)号：US11764258B2

公开(公告)日：2023-09-19

申请号：US17108543

申请日：2020-12-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Brett T. Cucci ,  Siva P. Adusumilli ,  Johnatan A. Kantarovsky ,  Claire E. Kardos ,  Sen Liu

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/7682

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap isolation structures and methods of manufacture. The structure includes: a bulk substrate material; a first airgap isolation structure in the bulk substrate material and having a first aspect ratio; and a second airgap isolation structure in the bulk substrate material and having a second aspect ratio different from the first aspect ratio.

公开(公告)号：US11728348B2

公开(公告)日：2023-08-15

申请号：US17498241

申请日：2021-10-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli ,  Michel J. Abou-Khalil

IPC: H01L23/31 ,  H01L27/12 ,  H01L27/02 ,  H01L29/16 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10 ,  H01L29/40 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L21/84 ,  H01L21/3065 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/1087 ,  H01L29/16 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/665

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked field effect transistors and methods of manufacture. The structure includes: at least one lower gate structure on a bottom of a trench formed in substrate material; insulator material partially filling trench and over the at least one lower gate structure; an epitaxial material on the insulator material and isolated from sidewalls of the trench; and at least one upper gate structure stacked vertically above the at least one lower gate structure and located on the epitaxial material.

公开(公告)号：US20230125584A1

公开(公告)日：2023-04-27

申请号：US17934220

申请日：2022-09-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

IPC: H01L21/02

Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.