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公开(公告)号：DE69028825T2
公开(公告)日：1997-02-13
申请号：DE69028825
申请日：1990-06-20
Applicant: HAMAMATSU PHOTONICS KK
Inventor： MIZUSHIMA YOSHIHIKO , NAKAJIMA KAZUTOSHI , HIROHATA TORU , IIDA TAKASHI , WARASHINA YOSHIHISA , SUZUKI TOMOKO , KAN HIROFUMI
Abstract: SUM and CARRY output signals of a first optical half adder are provided to one input terminal of a second optical half adder and an optical latch memory, respectively, and an output signal of the optical latch memory is provided to the other input terminal of the second optical half adder. Input and output of the two optical half adders and optical latch memory are performed through an optical signal. Each optical half adder includes two light-receiving elements each having a symmetrical electrode arrangement in which two Schottky junctions are connected to each other opposite in polarity, and peripheral elements of resistors, a capacitor and an amplifier. The optical latch memory is an optical flip-flop memory in which a high-speed light-receiving element produces an electric signal in response to an input optical signals, and a high-speed light-emitting element produces, in response to the electric signal guided from the light-receiving element, feed-back light to be applied to the light-receiving element and an output optical signal.
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公开(公告)号：DE69028825D1
公开(公告)日：1996-11-14
申请号：DE69028825
申请日：1990-06-20
Applicant: HAMAMATSU PHOTONICS KK
Inventor： MIZUSHIMA YOSHIHIKO , NAKAJIMA KAZUTOSHI , HIROHATA TORU , IIDA TAKASHI , WARASHINA YOSHIHISA , SUZUKI TOMOKO , KAN HIROFUMI
Abstract: SUM and CARRY output signals of a first optical half adder are provided to one input terminal of a second optical half adder and an optical latch memory, respectively, and an output signal of the optical latch memory is provided to the other input terminal of the second optical half adder. Input and output of the two optical half adders and optical latch memory are performed through an optical signal. Each optical half adder includes two light-receiving elements each having a symmetrical electrode arrangement in which two Schottky junctions are connected to each other opposite in polarity, and peripheral elements of resistors, a capacitor and an amplifier. The optical latch memory is an optical flip-flop memory in which a high-speed light-receiving element produces an electric signal in response to an input optical signals, and a high-speed light-emitting element produces, in response to the electric signal guided from the light-receiving element, feed-back light to be applied to the light-receiving element and an output optical signal.
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公开(公告)号：DE68911781D1
公开(公告)日：1994-02-10
申请号：DE68911781
申请日：1989-07-28
Applicant: HAMAMATSU PHOTONICS KK
Inventor： NAKAJIMA KAZUTOSHI , KAN HIROFUMI , SUGIMOTO KENICHI , MIZUSHIMA YOSHIHIKO , HIROHATA TORU , IIDA TAKASHI , WARASHINA YOSHIHISA
Abstract: An optical memory circuit comprises two photodetectors, and an intermediate signal conductor for connecting the two photodetectors, wherein the two photodetectors and the signal conductor are connected in series in a closed circuit, and the signal conductor has such capacitance that a time constant of a potential of the signal conductor has such a large value as allows charges to be stored in the signal conductor when an optical write signal is incident on one photodetector whereas allows stored charges to be released from the signal conductor when an optical read signal is incident on the other photodetector.
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公开(公告)号：DE68911781T2
公开(公告)日：1994-04-14
申请号：DE68911781
申请日：1989-07-28
Applicant: HAMAMATSU PHOTONICS KK
Inventor： NAKAJIMA KAZUTOSHI , KAN HIROFUMI , SUGIMOTO KENICHI , MIZUSHIMA YOSHIHIKO , HIROHATA TORU , IIDA TAKASHI , WARASHINA YOSHIHISA
Abstract: An optical memory circuit comprises two photodetectors, and an intermediate signal conductor for connecting the two photodetectors, wherein the two photodetectors and the signal conductor are connected in series in a closed circuit, and the signal conductor has such capacitance that a time constant of a potential of the signal conductor has such a large value as allows charges to be stored in the signal conductor when an optical write signal is incident on one photodetector whereas allows stored charges to be released from the signal conductor when an optical read signal is incident on the other photodetector.
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公开(公告)号：DE3939300A1
公开(公告)日：1990-10-11
申请号：DE3939300
申请日：1989-11-28
Applicant: HAMAMATSU PHOTONICS KK
Inventor： MIZUSHIMA YOSHIHIKO , NAKAJIMA KAZUTOSHI , HIROHATA TORU , IIDA TAKASHI , WARASHINA YOSHIHISA , SUGIMOTO KENICHI , KAN HIROFUMI
IPC: H03K19/14
Abstract: A plurality of ultra-high speed light receiving elements are provided each of which has two rectifier junctions being connected to each other opposite in polarity and has a substantially symmetrical electrode arrangement. A bias voltage is applied to each of the light receiving elements from one or a plurality of power sources. Electrical signals produced by the light receiving elements in response to input optical pulse signals are superposed on one another to produce one or a plurality of output electrical signals representing a predetermined logic operation with respect to the input optical pulse signals. Depending on the arrangement of its elements, the optical logic operation system functions as an OR circuit, AND circuit, NOT circuit, EXCLUSIVE OR circuit, or half-adder circuit.
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Patent Agency Ranking
公开(公告)号：EP1596233A4
公开(公告)日：2007-05-23
申请号：EP04712756
申请日：2004-02-19
Applicant: HAMAMATSU PHOTONICS KK
Inventor： HOSHINO YASUJI , IIDA TAKASHI , WARASHINA YOSHIHISA , TABATA KEI
CPC classification number: G02B6/423 , G02B6/4201 , G02B6/4214 , G02B6/4243 , G02B6/4249 , H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/00
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公开(公告)号：EP2403011A4
公开(公告)日：2013-03-20
申请号：EP10746105
申请日：2010-02-15
Applicant: HAMAMATSU PHOTONICS KK
Inventor： SAKAMOTO AKIRA , IIDA TAKASHI , YAMAMOTO KOEI , YAMAMURA KAZUHISA , NAGANO TERUMASA
IPC: H01L31/10 , H01L31/0236
CPC classification number: H01L31/02366 , H01L27/1446 , H01L31/0236 , H01L31/02363 , H01L31/035281 , H01L31/1804 , Y02E10/547 , Y02P70/521
Abstract: Prepared is an n - type semiconductor substrate 1 having a first principal surface 1a and a second principal surface 1b opposed to each other, and having a p + type semiconductor region 3 formed on the first principal surface 1a side. At least a region opposed to the p + type semiconductor region 3 in the second principal surface 1a of the n - type semiconductor substrate 1 is irradiated with a pulsed laser beam to form an irregular asperity 10. After formation of the irregular asperity 10, an accumulation layer 11 with an impurity concentration higher than that of the n - type semiconductor substrate 1 is formed on the second principal surface 1a side of the n - type semiconductor substrate 1. After formation of the accumulation layer 11, the n - type semiconductor substrate 1 is subjected to a thermal treatment.
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公开(公告)号：EP2072978A4
公开(公告)日：2014-01-08
申请号：EP08765177
申请日：2008-06-05
Applicant: HAMAMATSU PHOTONICS KK
Inventor： SUZUKI TOMOFUMI , SHIBAYAMA KATSUMI , IIDA TAKASHI , YOKINO TAKAFUMI , ITO MASASHI , TEICHMANN HELMUT , HILLER DIETMAR , STARKER ULRICH
CPC classification number: G01J3/14 , G01J3/02 , G01J3/0256
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公开(公告)号：JP2008053380A
公开(公告)日：2008-03-06
申请号：JP2006227064
申请日：2006-08-23
Applicant: Hamamatsu Photonics Kk , 浜松ホトニクス株式会社
Inventor： IIDA TAKASHI , TEI USHIN , SUGA HIROBUMI
IPC: H01S5/40
Abstract: PROBLEM TO BE SOLVED: To provide a laser device manufactured by a specific structure so as to compose laser beams from a plurality of laser arrays to obtain a high output. SOLUTION: A first laser unit 3 for outputting first output laser beams, and a second laser unit 4 which has a mounting part of a different thickness from the first laser unit 3 for outputting second output laser beams in a direction perpendicular to the first output laser beams, are mounted on a metallic base 9 via insulating sheets 13, 21, respectively, a mirror 42 for reflecting a progressive direction of the second output laser beams to the identical direction to the first output laser beams is mounted thereon, and the first and second laser units 3, 4 are electrically series-connected by a wiring to constitute the laser device 1. Thus, even when the laser beams from the plurality of laser arrays are composed to obtain a sufficiently high output, a cooling can be suitably performed, and when an operator touches the device, he/she can be prevented from receiving an electric shock. COPYRIGHT: (C)2008,JPO&INPIT
Abstract translation: 要解决的问题：提供通过特定结构制造的激光装置，以便组成来自多个激光阵列的激光束以获得高输出。 解决方案：用于输出第一输出激光束的第一激光单元3和具有与第一激光单元3不同厚度的安装部分的第二激光单元4，用于沿垂直于第一激光单元3的方向输出第二输出激光束 第一输出激光束分别通过绝缘片13,21安装在金属基座9上，用于将第二输出激光束的逐行方向反射到与第一输出激光束相同方向的反射镜42安装在其上， 第一激光单元3,4和第二激光单元4通过布线电连接以构成激光装置1.因此，即使组合来自多个激光阵列的激光以获得足够高的输出，也可以是冷却 适当地执行，并且当操作者触摸该装置时，可以防止他/她受到电击。 版权所有（C）2008，JPO＆INPIT
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公开(公告)号：JPH07129267A
公开(公告)日：1995-05-19
申请号：JP27838593
申请日：1993-11-08
Applicant: HAMAMATSU PHOTONICS KK
Inventor： MIZUSHIMA YOSHIHIKO , NAKAJIMA KAZUTOSHI , HIROHATA TORU , IIDA TAKASHI , WARASHINA SADAHISA , SUGIMOTO KENICHI , SUZUKI TOMOKO , SUGA HIROBUMI
Abstract: PURPOSE:To provide the photoelectric computing element which can obtain the product of light signals directly and also obtain the sum of obtained products fast through simple circuit constitution. CONSTITUTION:Pairs of semiconductor photodetecting elements 11, 12... 1n,. and semiconductor photodetecting elements 21, 22...2n in substantially right-left symmetrical electrode structure are regarded as unit circuits, and a bias voltage 3 is applied to one-terminal sides of the respective unit circuits. Further, the output-side terminals of the respective unit circuits are connected into one to obtain an output terminal 4. When light signals are made incident on the semiconductor surfaces between the electrodes of the respective photodetecting elements while bias voltages are applied between the electrodes of the respective photodetecting elements, the input light signals are converted photoelectrically into current signals. The photoelectric conversion is performed by the respective unit circuits at the same time, and current outputs from the respective unit circuits appear at the output terminal 4 at the same time. Therefore, products xi and yi outputted by the unit circuits are added together at the output terminal 4 and the sum SIGMAxiyi of respective products is obtained at the terminal 4.
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