公开(公告)号：US6278339B2

公开(公告)日：2001-08-21

申请号：US73567900

申请日：2000-12-13

Applicant: IBM

Inventor： ABADEER WAGDI W ,  CONNOR JOHN ,  HANSEN PATRICK R

IPC: H04L25/02 ,  H03H7/38 ,  H03H7/40

CPC classification number: H04L25/0278

Abstract: An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit. Optionally, the impedance matching network further comprises a control circuit which detects overshoots and undershoots on the driver circuit output and provides a control current proportional to the magnitude of overshoots and undershoots to an electromagnetic adjustment mechanism which provides a linear adjustment to the moveable stub proportional to the control current.

公开(公告)号：EP2084756A4

公开(公告)日：2012-02-15

申请号：EP07863787

申请日：2007-11-01

Applicant: IBM

Inventor： ABADEER WAGDI W

IPC: H01L31/062

CPC classification number: H04N5/374 ,  H01L27/14609 ,  H01L27/14645 ,  H04N5/361 ,  H04N5/3741

公开(公告)号：EP1678764A4

公开(公告)日：2011-03-02

申请号：EP04817244

申请日：2004-10-04

Applicant: IBM

Inventor： ABADEER WAGDI W ,  FIFIELD JOHN A ,  TONTI WILLIAM R

IPC: H01L27/12 ,  H01L21/82 ,  H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

公开(公告)号：EP1581968A4

公开(公告)日：2007-04-18

申请号：EP02808339

申请日：2002-12-20

Applicant: IBM

Inventor： RANKIN JED H ,  ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J JR ,  FRIED DAVID M

IPC: H01L23/525 ,  H01L21/82 ,  H01L21/84 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).

公开(公告)号：JP2007158342A

公开(公告)日：2007-06-21

申请号：JP2006326844

申请日：2006-12-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ABADEER WAGDI W ,  HAUSER MICHAEL J ,  ADKISSON JAMES W ,  RANKIN JED H ,  GAUTHIER ROBERT J JR ,  CHATTY KIRAN V ,  JEFFREY SCOTT BROWN ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/14 ,  H01L31/12

CPC classification number: H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of executing an electrical function such as a fusing operation by activation through a chip-embedded photodiode through spectrally selected external light activation, a corresponding structure, and a corresponding circuit. SOLUTION: In conjunction with additional circuit elements to an integrated circuit, incident light with specific intensity/wave length characteristics performs the implementation of repairs. More specifically, failing circuit elements are replaced with redundant ones for yield and/or reliability, and, after a packaged chip is placed in the system, the incident light makes an ESD protection device be disconnected from input pad. No additional pins on the package are necessary. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过光谱选择的外部光激活，对应的结构和相应的电路来通过芯片嵌入式光电二极管的激活来执行诸如定影操作之类的电功能的方法。

解决方案：结合集成电路的附加电路元件，具有特定强度/波长特性的入射光执行维修。 更具体地，用于产生和/或可靠性的冗余电路元件被替换，并且在将封装芯片放置在系统中之后，入射光使得ESD保护装置与输入焊盘断开连接。 不需要额外的引脚。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004088101A

公开(公告)日：2004-03-18

申请号：JP2003287197

申请日：2003-08-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ABADEER WAGDI W ,  BROWN JEFFREY S ,  FRIED DAVID M ,  GAUTHIER JR ROBERT J ,  EDWARD J NOWAKU ,  RANKIN JED H ,  TONTI WILLIAM R

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

Abstract: PROBLEM TO BE SOLVED: To provide an improved manufacturing method of an integrated circuit which is made by incorporating both a FinFET and a thick-body device into a single chip. SOLUTION: This manufacturing method of a microelectronic circuit which is made by incorporating both a fin-type field-effect transistor (FinFET) 1801 and a thick-body device 1802 into a single chip can attain an efficiency higher than that of the conventional methods by utilizing common masks and processes. Reduction in the numbers of masks and processes is achieved by utilizing common masks and processes together with several reduction strategies. For example, a structure which usually accompanies a FinFET is formed on a side surface of a thick silicon mesa. A bulk of the silicon mesa is doped to connect to a body contact formed on the opposite side surface of the mesa. This invention also includes the FinFET, thick-body device, and a chip manufactured by the methods associated with the invention. COPYRIGHT: (C)2004,JPO

公开(公告)号：WO2005038869A3

公开(公告)日：2006-02-09

申请号：PCT/US2004032581

申请日：2004-10-04

Applicant: IBM ,  ABADEER WAGDI W ,  FIFIELD JOHN A ,  TONTI WILLIAM R

Inventor： ABADEER WAGDI W ,  FIFIELD JOHN A ,  TONTI WILLIAM R

IPC: H01L23/525 ,  H01L27/12 ,  H01L21/82 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit.

Abstract translation: 一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。 当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。 当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。 反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。 该电压差非常高，可以使用简单的感测电路容易地感测。

公开(公告)号：WO2008057939A2

公开(公告)日：2008-05-15

申请号：PCT/US2007083332

申请日：2007-11-01

Applicant: IBM ,  ABADEER WAGDI W

Inventor： ABADEER WAGDI W

IPC: H01L31/113

CPC classification number: H04N5/374 ,  H01L27/14609 ,  H01L27/14645 ,  H04N5/361 ,  H04N5/3741

Abstract: A CMOS image sensor and active pixel cell design 50, that provides an output signal representing an incident illumination light level that is adapted for time domain analysis. Thus, the noise sources associated with charge integration and the contribution of dark current to it, is avoided. The active pixel cell design implements only three FETs: a transfer device 53, a reset device 63, and an output transistor device 73, having one diffusion connected to a Row Select signal RS. In this mode of operation, use is made of the voltage decay at the photo diode to generate a pixel output VWB, at one diffusion of the output transistor device, which is a pulse with fixed amplitude independent of the incident illumination level. For use of an NFET output transistor device, the pulse width is an inverse function of the incident illumination level. For a PFET output transistor device, the output pulse has a time delay, from a reference signal, by an amount that is an inverse function of the incident illumination level.

Abstract translation: CMOS图像传感器和有源像素单元设计50，其提供表示适于时域分析的入射照明光水平的输出信号。 因此，避免了与电荷积分相关的噪声源和暗电流对其的贡献。 有源像素单元设计仅实现三个FET：传输设备53，复位设备63和输出晶体管器件73，其一个扩散连接到行选择信号RS。 在这种操作模式下，在输出晶体管器件的一个扩散处，使用光电二极管的电压衰减来产生像素输出VWB，输出晶体管器件是具有独立于入射照明电平的固定振幅的脉冲。 对于使用NFET输出晶体管器件，脉冲宽度是入射照明电平的反函数。 对于PFET输出晶体管器件，输出脉冲具有来自参考信号的时间延迟与入射照明电平的反函数的量。

公开(公告)号：DE60236375D1

公开(公告)日：2010-06-24

申请号：DE60236375

申请日：2002-12-20

Applicant: IBM

Inventor： RANKIN JED H ,  ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J ,  FRIED DAVID M

IPC: H01L21/82 ,  H01L21/84 ,  H01L23/525 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12

公开(公告)号：AU2002368525A1

公开(公告)日：2004-07-22

申请号：AU2002368525

申请日：2002-12-20

Applicant: IBM

Inventor： ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J JR ,  FRIED DAVID M ,  RANKIN JED H

IPC: H01L21/82 ,  H01L21/84 ,  H01L23/525 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12 ,  H01L21/44