公开(公告)号：EP2419931A4

公开(公告)日：2012-04-04

申请号：EP10764802

申请日：2010-03-18

Applicant: IBM

Inventor： CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  LI JUNJUN ,  MUHAMAD MUJAHID

IPC: H01L27/02

CPC classification number: H01L27/0274 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1581968A4

公开(公告)日：2007-04-18

申请号：EP02808339

申请日：2002-12-20

Applicant: IBM

Inventor： RANKIN JED H ,  ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J JR ,  FRIED DAVID M

IPC: H01L23/525 ,  H01L21/82 ,  H01L21/84 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).

公开(公告)号：JP2007158342A

公开(公告)日：2007-06-21

申请号：JP2006326844

申请日：2006-12-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ABADEER WAGDI W ,  HAUSER MICHAEL J ,  ADKISSON JAMES W ,  RANKIN JED H ,  GAUTHIER ROBERT J JR ,  CHATTY KIRAN V ,  JEFFREY SCOTT BROWN ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/14 ,  H01L31/12

CPC classification number: H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of executing an electrical function such as a fusing operation by activation through a chip-embedded photodiode through spectrally selected external light activation, a corresponding structure, and a corresponding circuit. SOLUTION: In conjunction with additional circuit elements to an integrated circuit, incident light with specific intensity/wave length characteristics performs the implementation of repairs. More specifically, failing circuit elements are replaced with redundant ones for yield and/or reliability, and, after a packaged chip is placed in the system, the incident light makes an ESD protection device be disconnected from input pad. No additional pins on the package are necessary. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过光谱选择的外部光激活，对应的结构和相应的电路来通过芯片嵌入式光电二极管的激活来执行诸如定影操作之类的电功能的方法。

解决方案：结合集成电路的附加电路元件，具有特定强度/波长特性的入射光执行维修。 更具体地，用于产生和/或可靠性的冗余电路元件被替换，并且在将封装芯片放置在系统中之后，入射光使得ESD保护装置与输入焊盘断开连接。 不需要额外的引脚。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2010120428A3

公开(公告)日：2011-01-13

申请号：PCT/US2010027774

申请日：2010-03-18

Applicant: IBM ,  CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  LI JUNJUN ,  MUHAMAD MUJAHID

Inventor： CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  LI JUNJUN ,  MUHAMAD MUJAHID

IPC: H01L23/60 ,  H01L21/336

CPC classification number: H01L27/0274 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit (200) includes a middle junction control circuit (250) that turns off a top NFET (225) of a stacked NFET electrostatic discharge (ESD) protection circuit (pad 215, ground 220, top NFET 225, bottom NFET 230, top resistor 235, and bottom resistor 240) during an ESD event.

Abstract translation: 公开了用于容错和故障安全设计的强大的ESD保护电路，方法和设计结构。 一个电路（200）包括一个中间结点控制电路（250），该中间结点控制电路（250）将堆叠的NFET静电放电（ESD）保护电路（焊盘215，接地220，顶部NFET 225，底部NFET 230，顶部）的顶部NFET（225） 电阻器235和底部电阻器240）。

公开(公告)号：CA2755284C

公开(公告)日：2017-11-21

申请号：CA2755284

申请日：2010-03-18

Applicant: IBM

Inventor： CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  LI JUNJUN ,  MUHAMAD MUJAHID

IPC: H01L23/60 ,  H01L21/336

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are dis-closed. A circuit (200) includes a middle junction control circuit (250) that turns off a top NFET (225) of a stacked NFET electrostatic discharge (ESD) protection circuit (pad 215, ground 220, top NFET 225, bottom NFET 230, top resistor 235, and bottom resistor 240) during an ESD event.

公开(公告)号：AU2010236920B2

公开(公告)日：2014-02-27

申请号：AU2010236920

申请日：2010-03-18

Applicant: IBM

Inventor： CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  LI JUNJUN ,  MUHAMAD MUJAHID

IPC: H01L21/336 ,  H01L23/60

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit (200) includes a middle junction control circuit (250) that turns off a top NFET (225) of a stacked NFET electrostatic discharge (ESD) protection circuit (pad 215, ground 220, top NFET 225, bottom NFET 230, top resistor 235, and bottom resistor 240) during an ESD event.

公开(公告)号：AU2010236920A1

公开(公告)日：2011-08-25

申请号：AU2010236920

申请日：2010-03-18

Applicant: IBM

Inventor： CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  JUNJUN LI ,  MUJAHID MUHAMAD

IPC: H01L21/336 ,  H01L23/60

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit (200) includes a middle junction control circuit (250) that turns off a top NFET (225) of a stacked NFET electrostatic discharge (ESD) protection circuit (pad 215, ground 220, top NFET 225, bottom NFET 230, top resistor 235, and bottom resistor 240) during an ESD event.

公开(公告)号：DE60236375D1

公开(公告)日：2010-06-24

申请号：DE60236375

申请日：2002-12-20

Applicant: IBM

Inventor： RANKIN JED H ,  ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J ,  FRIED DAVID M

IPC: H01L21/82 ,  H01L21/84 ,  H01L23/525 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12

公开(公告)号：AU2002368525A1

公开(公告)日：2004-07-22

申请号：AU2002368525

申请日：2002-12-20

Applicant: IBM

Inventor： ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J JR ,  FRIED DAVID M ,  RANKIN JED H

IPC: H01L21/82 ,  H01L21/84 ,  H01L23/525 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12 ,  H01L21/44

公开(公告)号：DE112012000233T5

公开(公告)日：2013-11-28

申请号：DE112012000233

申请日：2012-01-06

Applicant: IBM

Inventor： ABOU-KHALIL MICHAEL J ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  LI JUNJUN

IPC: H01L29/66

Abstract: Hierin werden gesteuerte Silicium-Gleichrichter (SCR), Herstellungsverfahren und Entwicklungsstrukturen offenbart. Das Verfahren weist das Bilden einer gemeinsamen P-Wanne (12) auf einer vergrabenen Isolatorschicht (28b) eines Silicium-auf-Isolator(SOI)-Wafers (28) auf. Das Verfahren weist ferner das Bilden einer Vielzahl von gesteuerten Silicium-Gleichrichtern (SCR) (10) in der gemeinsamen P-Wanne auf, so dass N+-Diffusionskathoden (20) von jedem aus der Vielzahl von SCRs durch die gemeinsame P-Wanne zusammengekoppelt sind.