公开(公告)号：DE2453578A1

公开(公告)日：1975-07-10

申请号：DE2453578

申请日：1974-11-12

Applicant: IBM

Inventor： BAKER THEODORE HARRIS ,  STEVENS RICHARD CHARLES ,  TZOU ALBERT JI-SHOU

IPC: H01L21/66 ,  G01R27/02 ,  G01R31/26 ,  H01L21/027 ,  H01L21/28

公开(公告)号：DE2453528A1

公开(公告)日：1975-07-10

申请号：DE2453528

申请日：1974-11-12

Applicant: IBM

Inventor： BAKER THEODORE HARRIS ,  GHAFGHAICHI MAJID

IPC: H05K3/46 ,  H01L21/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/31 ,  H01L21/316 ,  H01L21/3213

Abstract: In the fabrication of integrated circuits, a method of forming openings through an insulative layer wherein a plurality of openings being formed through said insulative layer are subjected to two separate etching steps in order to insure that the opening is made.

公开(公告)号：DE2636971A1

公开(公告)日：1977-04-28

申请号：DE2636971

申请日：1976-08-17

Applicant: IBM

Inventor： BAKER THEODORE HARRIS ,  GHAFGHAICHI MAJID ,  STEVENS RICHARD CHARLES ,  WIMPFHEIMER HANS

IPC: H01L21/3213 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/82

Abstract: A method of planarizing an electrically insulative layer formed over a non-planar integrated circuit substrate having raised portions. After the electrically insulative layers are deposited over such substrate, the layer has elevations corresponding to the underlying raised portions of the substrate. A masking layer is formed on the electrically insulative layer having at least one opening therethrough coincident with an elevation in the insulative layer; this opening has smaller lateral dimensions than the coincident elevation, thereby facilitating alignment. The elevation in the insulative layer exposed in said at least one opening is then etched to the level of the unelevated portion of the layer, and the insulative layer is then resputtered for a period of time sufficient to planarize the remainder of such etched elevation to the level of the unelevated portions.

公开(公告)号：DE2243809A1

公开(公告)日：1973-05-10

申请号：DE2243809

申请日：1972-09-07

Applicant: IBM

Inventor： BAKER THEODORE HARRIS ,  GHAFGHAICHI MAJID ,  TOTTA PAUL ANTHONY

IPC: H05K13/02 ,  H01L21/02 ,  H01L21/60 ,  H01L21/822 ,  H01L23/00 ,  H01L27/04 ,  H01L7/34

Abstract: 1393423 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 12 Sept 1972 [3 Nov 1971] 42279/72 Heading H1K Damage to the surface of a semi-conductor chip 21 due to impact by the edges and corners of other similar chips such as 22 during handling is reduced by arranging a plurality of suitably situated and dimensioned projections on the chip surface. Some of the projections 19 may be contact pads, and additional projections 18 may also be provided having the same height and composition (e.g. a solder bump on a Cr/Cu/ Au layer) on the contact pads 19. Preferably at least 75% of the chip surface area is protected against impact in this way, protection not being necessary in certain regions of the surface where circuit function would not be impaired by the effects of chip impacts.