公开(公告)号：US3668522A

公开(公告)日：1972-06-06

申请号：US3668522D

申请日：1968-12-09

Applicant: IBM

Inventor： GHAFGHAICHI MAJID

IPC: G01R29/02 ,  G01R31/26 ,  G01R31/22 ,  G01R27/04

CPC classification number: G01R31/2608 ,  G01R29/02

Abstract: Method and apparatus for characterizing the dynamic input impedance of a test element by measuring the rise-time degradation of an input waveform. A pulse having a very fast rise-time is supplied by a pulse generator and transmitted down two branches of a balanced transmission line. One leg of the balanced transmission line is connected to a sensing means while the other leg of the balanced transmission line is connected to a test element as well as the sensing means. Thus, the sensing means would receive two identical pulses but for the rise-time degradation of the pulse connected to the test element. The test element is characterized on the basis of this rise-time degradation.

Abstract translation: 通过测量输入波形的上升时间劣化来表征测试元件的动态输入阻抗的方法和装置。 具有非常快的上升时间的脉冲由脉冲发生器提供并且被传送到平衡传输线的两个分支。 平衡传输线的一条腿连接到感测装置，而平衡传输线的另一条腿连接到测试元件以及感测装置。 因此，感测装置将接收两个相同的脉冲，但是对于连接到测试元件的脉冲的上升时间劣化。 测试元件的特征在于这种上升时间退化。

公开(公告)号：US3922184A

公开(公告)日：1975-11-25

申请号：US42788773

申请日：1973-12-26

Applicant: IBM

Inventor： BAKER THEODORE H ,  GHAFGHAICHI MAJID

IPC: H05K3/46 ,  H01L21/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/31 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/308

CPC classification number: H01L21/31 ,  H01L21/00 ,  H01L21/316

Abstract: In the fabrication of integrated circuits, a method of forming openings through an insulative layer wherein a plurality of openings being formed through said insulative layer are subjected to two separate etching steps in order to insure that the opening is made. In the method, a layer of electrically insulative material is formed on a substrate. The layer is covered with a first photoresist mask having a plurality of openings. Then, a plurality of openings through the insulative layer coincident with the mask openings is made by applying a chemical etchant through the photoresist mask. The second photoresist mask having a plurality of openings coincident with the openings in the insulative layer is then formed on said layer; these openings in the second photoresist mask have smaller lateral dimensions than the openings in the insulative layer. Thus, the sides of the openings in the insulative layer are masked by photoresist. The chemical etchant is reapplied through the second photoresist mask. In this reapplication, any openings which may not have been fully etched through the insulative layer in the first etching step are now made. On the other hand, because the sides of completed openings are already masked by photoresist, there is no possibility of the reapplied etchant etching through the sides of such completed holes to overetch such holes.

Abstract translation: 在集成电路的制造中，通过绝缘层形成开口的方法，其中通过所述绝缘层形成的多个开口经受两个单独的蚀刻步骤，以确保形成开口。

公开(公告)号：CA1133146A

公开(公告)日：1982-10-05

申请号：CA337643

申请日：1979-10-15

Applicant: IBM

Inventor： BALYOZ JOHN ,  CHANG CHI S ,  FOX BARRY C ,  GHAFGHAICHI MAJID ,  JEN TEH-SEN ,  MOONEY DONALD B ,  PALMIERI JOHN A

IPC: H01L21/822 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H05K1/16 ,  H05K3/10

Abstract: MASTER IMAGE CHIP ORGANIZATION TECHNIQUE OR METHOD Semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of large scale integrated part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. This master image wiring structure makes it possible to personalize the power and signal wiring for a multiple power surface structure. The combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units (micro and macro) and signal and power wiring to facilitate improved density and performance. FI9-78-014

公开(公告)号：CA1024663A

公开(公告)日：1978-01-17

申请号：CA213806

申请日：1974-11-15

Applicant: IBM

Inventor： BAKER THEODORE H ,  GHAFGHAICHI MAJID

IPC: H05K3/46 ,  H01L21/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/31 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/308

Abstract: In the fabrication of integrated circuits, a method of forming openings through an insulative layer wherein a plurality of openings being formed through said insulative layer are subjected to two separate etching steps in order to insure that the opening is made.

公开(公告)号：DE2636971A1

公开(公告)日：1977-04-28

申请号：DE2636971

申请日：1976-08-17

Applicant: IBM

Inventor： BAKER THEODORE HARRIS ,  GHAFGHAICHI MAJID ,  STEVENS RICHARD CHARLES ,  WIMPFHEIMER HANS

IPC: H01L21/3213 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/82

Abstract: A method of planarizing an electrically insulative layer formed over a non-planar integrated circuit substrate having raised portions. After the electrically insulative layers are deposited over such substrate, the layer has elevations corresponding to the underlying raised portions of the substrate. A masking layer is formed on the electrically insulative layer having at least one opening therethrough coincident with an elevation in the insulative layer; this opening has smaller lateral dimensions than the coincident elevation, thereby facilitating alignment. The elevation in the insulative layer exposed in said at least one opening is then etched to the level of the unelevated portion of the layer, and the insulative layer is then resputtered for a period of time sufficient to planarize the remainder of such etched elevation to the level of the unelevated portions.

公开(公告)号：CA1120606A

公开(公告)日：1982-03-23

申请号：CA326113

申请日：1979-04-23

Applicant: IBM

Inventor： BALYOZ JOHN ,  CHANG CHI S ,  FOX BARRY C ,  GHAFGHAICHI MAJID ,  JEN TEH-SEN ,  MOONEY DONALD B ,  PALMIERI JOHN A

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H01L27/10

Abstract: Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices. In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.

公开(公告)号：CA1067038A

公开(公告)日：1979-11-27

申请号：CA263201

申请日：1976-10-08

Applicant: IBM

Inventor： BAKER THEODORE H ,  GHAFGHAICHI MAJID ,  STEVENS RICHARD C ,  WIMPFHEIMER HANS

IPC: H01L21/3213 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/3205 ,  C23C15/00

Abstract: PLANARIZING INSULATIVE LAYERS BY RESPUTTERING A method of planarizing an electrically insulative layer formed over a non-planar integrated circuit substrate having raised portions. After the electrically insulative layers are deposited over such substrate, the layer has elevations corresponding to the underlying raised portions of the substrate. A masking layer is formed on the electrically insulative layer having at least one opening therethrough coincident with an elevation in the insulative layer; this opening has smaller lateral dimensions than the coincident elevation, thereby facilitating alignment. The elevation in the insulative layer exposed in said at least one opening is then etched to the level of the unelevated portion of the layer, and the insulative layer is then resputtered for a period of time sufficient to planarize the remainder of such etched elevation to the level of the unelevated portions.

公开(公告)号：CA964771A

公开(公告)日：1975-03-18

申请号：CA135898

申请日：1972-03-01

Applicant: IBM

Inventor： BAKER THEODORE H ,  GHAFGHAICHI MAJID ,  TUMAN DANIEL

IPC: H01L21/00 ,  H01L21/60 ,  H01L27/00

公开(公告)号：CA1111570A

公开(公告)日：1981-10-27

申请号：CA307591

申请日：1978-07-18

Applicant: IBM

Inventor： DALAL HORMAZDYAR M ,  GHAFGHAICHI MAJID ,  KASPRZAK LUCIAN A ,  WIMPFHEIMER HANS

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L21/338 ,  H01L21/60 ,  H01L23/532 ,  H01L29/43 ,  H01L29/45 ,  H01L29/47 ,  H01L29/872 ,  H01L29/18

Abstract: TANTALUM SEMICONDUCTOR CONTACTS AND METHOD FOR FABRICATING SAME A silicon semiconductor device having contacts which include tantalum. The tantalum is useful in particular for fabricating Schottky barrier diodes having a low barrier height. The method includes: precleaning the silicon substrate prior to depositing the tantalum; depositing the tantalum at low pressure and low substrate temperature to avoid oxidation of the tantalum; and sintering the contact to reduce any interfacial charges and films remaining between the silicon and tantalum. When a metal which reacts with silicon during processing, such as aluminum, is used as interconnection metallurgy, a layer of chrome must be deposited between the tantalum and aluminum.

公开(公告)号：FR2328285A1

公开(公告)日：1977-05-13

申请号：FR7626314

申请日：1976-08-25

Applicant: IBM

Inventor： BAKER THEODORE H ,  GHAFGHAICHI MAJID ,  STEVENS RICHARD C ,  WIMPFHEIMER HANS

IPC: H01L21/3213 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/314 ,  H01L21/94

Abstract: A method of planarizing an electrically insulative layer formed over a non-planar integrated circuit substrate having raised portions. After the electrically insulative layers are deposited over such substrate, the layer has elevations corresponding to the underlying raised portions of the substrate. A masking layer is formed on the electrically insulative layer having at least one opening therethrough coincident with an elevation in the insulative layer; this opening has smaller lateral dimensions than the coincident elevation, thereby facilitating alignment. The elevation in the insulative layer exposed in said at least one opening is then etched to the level of the unelevated portion of the layer, and the insulative layer is then resputtered for a period of time sufficient to planarize the remainder of such etched elevation to the level of the unelevated portions.