公开(公告)号：CA1184308A

公开(公告)日：1985-03-19

申请号：CA425351

申请日：1983-04-06

Applicant: IBM

Inventor： BANNON ROBERT D ,  BHANSALI MAHENDRA M ,  CHISHOLM DOUGLAS R ,  FINNEY DAMON W ,  MINNICH WALTER D ,  SUAREZ GUSTAVO A

IPC: G06F11/10 ,  G06F12/16 ,  G06F11/00

Abstract: TRUE SINGLE ERROR CORRECTION SYSTEM A scheme for true error correction and multiple bit failure detection for a memory system using multiple data bits per chip. An H-Matrix results in syndrome generation of bits that are unique for single bit failures that will not match syndromes generated by multiple bit failures. All multiple bit failures are detected without miscorrecting any single bits that have not failed. Single pass logic employs all syndromes in parallel inputs to determine the presence of a single bit failure for subsequent correction and also detects the presence of multiple bit failures.

公开(公告)号：CA1159961A

公开(公告)日：1984-01-03

申请号：CA378621

申请日：1981-05-29

Applicant: IBM

Inventor： BANNON ROBERT D ,  BHANSALI MAHENDRA M

IPC: H03M13/00 ,  G06F11/00 ,  G06F11/10

Abstract: IBM Docket No. BC 9-80-005 An error correcting code mechanism for SEC-DED (16, 21) or (8, 12) code to correct data bit errors caused by alpha particle impingement into high density storage units. The data word is read into and out of a high density storage unit and generated check bits are stored in low density storage immune to alpha particle radiation. Data bits and check bits, addressed in parallel are read out to error detecting and correcting circuits to determine the existence of an error only in a data bit and correct the state of the erroneous bit. The number of check bits and required parity checking circuitry is reduced since no error checking of check bits, presumed to always be correct because of the use of low density storage occurs.