公开(公告)号：CA1184308A

公开(公告)日：1985-03-19

申请号：CA425351

申请日：1983-04-06

Applicant: IBM

Inventor： BANNON ROBERT D ,  BHANSALI MAHENDRA M ,  CHISHOLM DOUGLAS R ,  FINNEY DAMON W ,  MINNICH WALTER D ,  SUAREZ GUSTAVO A

IPC: G06F11/10 ,  G06F12/16 ,  G06F11/00

Abstract: TRUE SINGLE ERROR CORRECTION SYSTEM A scheme for true error correction and multiple bit failure detection for a memory system using multiple data bits per chip. An H-Matrix results in syndrome generation of bits that are unique for single bit failures that will not match syndromes generated by multiple bit failures. All multiple bit failures are detected without miscorrecting any single bits that have not failed. Single pass logic employs all syndromes in parallel inputs to determine the presence of a single bit failure for subsequent correction and also detects the presence of multiple bit failures.

公开(公告)号：DE69620497T2

公开(公告)日：2003-12-18

申请号：DE69620497

申请日：1996-01-25

Applicant: IBM

Inventor： ANNAPAREDDY NARASIMHAREDDY L ,  FINNEY DAMON W ,  JENKINS MICHAEL OWEN ,  KESSLER LARRY BURTON ,  LANG DONALD JOHN ,  MORA DAVID NICK ,  LIANG SONG CHYAU ,  PLOMGREN DAVID ARTHUR ,  URBISCI PETER P ,  WALLS ANDREW D

IPC: G06F15/173 ,  G06F1/18 ,  G06F13/40

Abstract: An interconnection network is proposed which preferably comprises a pair of backplanes 10, 12 for receiving X pluggable node cards. The pair of backplanes include x backplane connector groups, each backplane connector group adapted to receive mating connectors from a pluggable node card. Each backplane connector group preferably includes X/2 connectors. A first backplane 10 includes first permanent wiring 24, 26, 28, 30, 32, 34 which interconnects a first subset of pairs of connectors between backplane connector groups. A second backplane 12 includes second permanent wiring 42, 44, 46, 48, 50, 52 which interconnects a second subset of pairs of connectors between backplane connector groups. The first permanent wiring and second permanent wiring connect complementary subsets of pairs of the connectors. A plurality of node cards, each including a card connector group, pluggably mate with the backplane connector groups. Each node card further includes a frontal connector that is adapted to receive a cable interconnection. Each node card includes a processor and a switch module which simultaneously connects the processor to at least plural connectors of a backplane connector group.

公开(公告)号：DE69620497D1

公开(公告)日：2002-05-16

申请号：DE69620497

申请日：1996-01-25

Applicant: IBM

Inventor： ANNAPAREDDY NARASIMHAREDDY L ,  FINNEY DAMON W ,  JENKINS MICHAEL OWEN ,  KESSLER LARRY BURTON ,  LANG DONALD JOHN ,  MORA DAVID NICK ,  LIANG SONG CHYAU ,  PLOMGREN DAVID ARTHUR ,  URBISCI PETER P ,  WALLS ANDREW D

IPC: G06F15/173 ,  G06F1/18 ,  G06F13/40

Abstract: An interconnection network is proposed which preferably comprises a pair of backplanes 10, 12 for receiving X pluggable node cards. The pair of backplanes include x backplane connector groups, each backplane connector group adapted to receive mating connectors from a pluggable node card. Each backplane connector group preferably includes X/2 connectors. A first backplane 10 includes first permanent wiring 24, 26, 28, 30, 32, 34 which interconnects a first subset of pairs of connectors between backplane connector groups. A second backplane 12 includes second permanent wiring 42, 44, 46, 48, 50, 52 which interconnects a second subset of pairs of connectors between backplane connector groups. The first permanent wiring and second permanent wiring connect complementary subsets of pairs of the connectors. A plurality of node cards, each including a card connector group, pluggably mate with the backplane connector groups. Each node card further includes a frontal connector that is adapted to receive a cable interconnection. Each node card includes a processor and a switch module which simultaneously connects the processor to at least plural connectors of a backplane connector group.

公开(公告)号：SG60155A1

公开(公告)日：1999-02-22

申请号：SG1997004102

申请日：1997-11-20

Applicant: IBM

Inventor： BENHASE MICHAEL T ,  BRADY JAMES THOMAS ,  FINNEY DAMON W ,  HARTUNG MICHAEL H ,  KO MICHAEL ANTHONY ,  LANG DONALD J ,  MENON JAISHANKAR MOOTHEDATH

IPC: G06F3/06 ,  G06F13/38 ,  G06F12/02

Abstract: A method enables a host processor, which employs variable length (VL) records, to communicate with disk storage which employs fixed length (FL) sectors for storage of the VL records. The method comprises the steps of: a) deriving a first control data structure for an update VL record, the first control data structure including information describing segments of the update VL record; b) determining a disk track that includes a FL sector wherein am old VL record commences that corresponds to the update VL record; c) reading each FL sector in the disk track and creating a control data structure which includes information describing each VL record stored in the disk track; d) substituting in a control data structure for the old VL record that corresponds to the update VL record, information regarding update data from the first control data structure; e) recording in the disk track, data indicated by each control data structure determined in steps c) and d); and f) if the old VL record ends at other than a sector break of a FL sector, reblocking VL records into FL sectors which are recorded thereafter on the disk track. The invention also enables a read action to be accomplished in one rotation of a disk even though it commences at a FL sector that is not at the beginning of a VL record to be accessed.