公开(公告)号：US3111648A

公开(公告)日：1963-11-19

申请号：US1889560

申请日：1960-03-31

Applicant: IBM

Inventor： MARSH ELLIOTT R ,  MINNICH WALTER D

IPC: G06F9/30 ,  G06F9/355

CPC classification number: G06F9/355 ,  G06F9/30025

公开(公告)号：CA1184308A

公开(公告)日：1985-03-19

申请号：CA425351

申请日：1983-04-06

Applicant: IBM

Inventor： BANNON ROBERT D ,  BHANSALI MAHENDRA M ,  CHISHOLM DOUGLAS R ,  FINNEY DAMON W ,  MINNICH WALTER D ,  SUAREZ GUSTAVO A

IPC: G06F11/10 ,  G06F12/16 ,  G06F11/00

Abstract: TRUE SINGLE ERROR CORRECTION SYSTEM A scheme for true error correction and multiple bit failure detection for a memory system using multiple data bits per chip. An H-Matrix results in syndrome generation of bits that are unique for single bit failures that will not match syndromes generated by multiple bit failures. All multiple bit failures are detected without miscorrecting any single bits that have not failed. Single pass logic employs all syndromes in parallel inputs to determine the presence of a single bit failure for subsequent correction and also detects the presence of multiple bit failures.