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    Multilayer insulation integrated circuit structure
    1.
    发明授权
    Multilayer insulation integrated circuit structure 失效
    多层绝缘集成电路结构

    公开(公告)号：US3877051A

    公开(公告)日：1975-04-08

    申请号：US29872972

    申请日：1972-10-18

    Applicant: IBM

    Inventor： CALHOUN HARRY C ,  FREED LARRY E ,  KAUFMAN CARL L

    IPC: H01L21/00 ,  H01L23/485 ,  H01L23/522 ,  H01L19/00

    CPC classification number: H01L23/485 ,  H01L21/00 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/98 ,  H01L2924/00

    Abstract: A planar semiconductor integrated circuit chip structure containing a planar surface from which a plurality of regions of different types and concentrations of conductivity-determining impurities extends into the chip to provide the active and passive devices of the circuit. The surface is passivated with an insulative structure containing at least two layers with a metallization pattern for interconnecting the integrated circuit devices formed on the first layer and via holes passing through the second or upper layer into contact with various portions of this metallization pattern. The via holes are arranged so that a majority of the holes are disposed above surface regions having such impurity types and concentrations that would form Schottky barrier contacts with the metal of contacts formed in said via holes. Accordingly, if during the formation of the via holes by etching through the second layer, there is an attendant further etching through the first layer to the surface of a semiconductor region, said region will form a Schottky barrier contact with the metal deposited in the via holes, which contact will act to prevent a short circuit between the metallization and the surface region.

    Abstract translation: 一种平面半导体集成电路芯片结构，其包含不同类型和多个导电性确定杂质的多个区域从该平面表面延伸到芯片中以提供该电路的有源和无源器件。 表面被绝缘结构钝化，其中包含至少两层的金属化图案，用于将形成在第一层上的集成电路器件和穿过第二层或上层的通孔与该金属化图案的各个部分接触。 通孔布置成使得大部分孔布置在具有这样的杂质类型和浓度的表面区域上方，该杂质类型和浓度将与形成在所述通孔中的触点的金属形成肖特基势垒接触。 因此，如果在通过蚀刻通过第二层形成通路孔期间，伴随着进一步的蚀刻通过第一层到半导体区域的表面，所述区域将与沉积在通孔中的金属形成肖特基势垒接触 该接触件将起作用以防止金属化和表面区域之间的短路。

    SIMPLIFIED COMPLEMENTARY TRANSISTOR PROCESS FOR MAKING ENHANCED GAIN LATERAL TRANSISTOR
    2.
    发明专利
    SIMPLIFIED COMPLEMENTARY TRANSISTOR PROCESS FOR MAKING ENHANCED GAIN LATERAL TRANSISTOR 未知

    公开(公告)号：CA1053376A

    公开(公告)日：1979-04-24

    申请号：CA266527

    申请日：1976-11-24

    Applicant: IBM

    Inventor： ANTIPOV IGOR ,  CALHOUN HARRY C

    IPC: H01L21/22 ,  H01L21/331 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/73 ,  H01L21/74

    Abstract: SIMPLIFIED COMPLEMENTARY TRANSISTOR PROCESS FOR MAKING ENHANCED GAIN LATERAL TRANSISTOR A process for producing simultaneously an NPN vertical bipolar transistor and a PNP lateral bipolar transistor on a recessed oxide-isolated epitaxial layer. An N+ buried layer is placed in the P- substrate beneath each transistor. P+ regions then are placed in the substrate underneath (or optionally in lieu of) the later formed recessed oxide and underneath the emitter region of each later formed lateral transistor. An N type epitaxial layer is deposited over the structure and the previously formed N+ and P+ substrate regions are outdiffused into the epitaxial layer, the P+ regions outdiffusing to a greater extent. Recessed oxide isolation walls are made and P+ areas are introduced into the epitaxial layer to form the base of each NPN transistor and to form a collector and an extended depth emitter for each PNP transistor, said emitter reaching from the surface of the epitaxial layer to the underlying N+ buried layer. The transistors are completed in the usual manner.

    Vertical and complementary lateral transistors prodn. - in integrated semiconductor technology gives increased charge carrier injection
    4.
    发明专利
    Vertical and complementary lateral transistors prodn. - in integrated semiconductor technology gives increased charge carrier injection 未知

    公开(公告)号：FR2347777A1

    公开(公告)日：1977-11-04

    申请号：FR7629494

    申请日：1976-09-22

    Applicant: IBM

    Inventor： ANTIPOV IGOR ,  CALHOUN HARRY C

    IPC: H01L21/22 ,  H01L21/331 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/73 ,  H01L21/74

    Abstract: A substrate (I) of a first conductivity type is provided with highly doped zones (II) of the second conductivity type, which act as buried collector zone of a vertical and buried base zone of a complementary lateral transistor. Highly doped zones (III) of the first conductivity type are formed between (II) as insulation zone and in (II) of the lateral transistor as part of the emitter zone, which then diffuse more strongly into an epitaxial layer of the second conductivity type, grown on (I), than do (II). Highly doped zones (IV) of the first conductivity type are formed in the epitaxial layer as base of the vertical and collector and part of the emitter, extending to the surface of the epitaxial layer, of the lateral transistor. Finally, a highly doped emitter (V) of the second conductivity type is formed in the base of the vertical transistor. The injection of charge carriers through the emitter is increased selectively in the area between the emitter and collector of the lateral transistor. This is achieved without the use of additional process stages. At the same time, the vertical part of the emitter junction of the lateral transistor can be extended, so that a further increase in the amplification factor of this transistor can be produced. Pref. the first conductivity type is the p-type, the buried zones are doped with As and the zone acting as part of the emitter with B.

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