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    Method for forming a field effect device
    1.
    发明授权
    Method for forming a field effect device 失效
    用于形成场效应装置的方法

    公开(公告)号：US3899373A

    公开(公告)日：1975-08-12

    申请号：US47140174

    申请日：1974-05-20

    Applicant: IBM

    Inventor： ANTIPOV IGOR

    IPC: H01L29/78 ,  H01L21/00 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/00 ,  H01L29/417 ,  H01L21/265

    CPC classification number: H01L21/00 ,  H01L21/28525 ,  H01L29/00 ,  Y10S148/053 ,  Y10S148/117 ,  Y10S148/122

    Abstract: A method for fabricating an insulated gate field effect transistor device which results in a doped polysilicon gate electrode which gate structure can be used for additional interconnection purposes. The method includes forming a thin blanket layer of an insulating material on a semiconductor substrate having source and drain regions and a surface insulating layer, depositing a blanket layer of polysilicon, depositing a blanket layer of Si3N4 and selectively removing leaving areas over the gate region and any desired interconnection pattern, oxidizing the exposed areas of the polysilicon layer, removing the remaining areas of Si3N4, and fabricating a passivation layer and an interconnection metallurgy system on the surface.

    Abstract translation: 一种用于制造绝缘栅场效应晶体管器件的方法，其导致掺杂多晶硅栅电极，栅极结构可用于额外的互连目的。 该方法包括在具有源极和漏极区域的半导体衬底上形成绝缘材料的薄橡皮布层和表面绝缘层，沉积多晶硅的覆盖层，沉积Si 3 N 4的覆盖层并选择性地去除栅极区域上的离开区域，以及 任何期望的互连图案，氧化多晶硅层的暴露区域，去除Si3N4的剩余区域，以及在表面上制造钝化层和互连冶金系统。

    3.
    发明专利
    未知

    公开(公告)号：DE1901665A1

    公开(公告)日：1969-09-04

    申请号：DE1901665

    申请日：1969-01-14

    Applicant: IBM DEUTSCHLAND

    Inventor： ANTIPOV IGOR ,  FREIBERG IRVING ,  DE ZANDE CHARLES H VANDE ,  L WING WAILEY ,  H BERGER HORST

    IPC: H01L23/544 ,  H01L7/02

    Abstract: 1,247,583. Integrated circuit manufacture. INTERNATIONAL BUSINESS MACHINES CORP. 9 Jan., 1969 [15 Jan., 1968], No. 1378/69. Heading H1K. [Also in Division G1] In the manufacture of a great many integrated circuits in/on an N- epitaxial layer on a P- silicon substrate wafer some of the circuit sites are occupied by test patterns of one of two kinds. At some sites the test pattern is used to check device characteristics and at other sites a different test pattern is used to check metallization characteristics. Each test pattern is provided with as few terminals as possible consistent with the tests to be undertaken. Within a " device " test pattern diffusionformed junction isolation is used to produce islands in which transistors and resistors are formed in numbers and type equivalent to a typical " working " circuit though their interconnections differ. Considering Fig. 3, potential supplies and a voltmeter are connected to the terminals as shown and enable the dynamic characteristics of two NPN transistors 50, 52 to be checked in a " current-switch " circuit. Alternative external connections are used to measure the V BE of each of these transistors to see how closely matched they are. Resistor values may be checked by measurement of R E and R c . R c , though not connected to a collector, represents what would be a typical collector resistor in one of the ordinary circuits on the wafer. Resistor isolation tests may be carried out on groups R1 c and R 1 E representing an average area of collector and emitter resistors in a typical integrated circuit; resistance measurements here also show up " pipes " resulting from the presence of pin holes in the oxide masking during the isolation diffusion step. R u is an underpass resistor, in normal circuits acting as a base resistor. A group of further underpass resistors R 1 u represent the other base resistors of a typical working circuit. Isolation tests are carried out on these since their isolation in working circuits is important. A group of transistors 54-66 represent the remaining transistors in a typical circuit; in the test pattern they are connected in parallel. Using these and the substrate connection 7 (formed on one of the diffused isolating walls), life tests and isolation checks are made on the important island isolation junction which, in a normal circuit, is subjected to the highest voltage. The metal interconnections on the top surface of the body lie on a silicon oxide layer and are themselves covered with glass passivation. The "metallization" pattern (Fig. 4, not shown) uses similar components but is not concerned with their interconnection. It has a large area metallization used to check pin-holes over a large representative area; connections to the N- epitaxial layer and to the P- substrate enable distinction to be made between pin-holes to the types. The pattern also connects to diffused resistors so that sheet resistivity measurements can be made with a four-point probe technique which also allows measurements of contact resistance. The application of resistance measurements to a narrow neck of metallization gives a cheek on the extent of etching used in forming the general interconnections. One terminal on top of the glass passivation has two separate connections through the glass to the metallization pattern to give a contact resistance check for the external connections to the metallization pattern. Collection of data from the test sites gives an estimate of the likely yield of working circuits on the wafer, shows up particular manufacturing faults &c and gives a guide to static and dynamic characteristics of the device in the working circuits.

    SIMPLIFIED COMPLEMENTARY TRANSISTOR PROCESS FOR MAKING ENHANCED GAIN LATERAL TRANSISTOR
    7.
    发明专利
    SIMPLIFIED COMPLEMENTARY TRANSISTOR PROCESS FOR MAKING ENHANCED GAIN LATERAL TRANSISTOR 未知

    公开(公告)号：CA1053376A

    公开(公告)日：1979-04-24

    申请号：CA266527

    申请日：1976-11-24

    Applicant: IBM

    Inventor： ANTIPOV IGOR ,  CALHOUN HARRY C

    IPC: H01L21/22 ,  H01L21/331 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/73 ,  H01L21/74

    Abstract: SIMPLIFIED COMPLEMENTARY TRANSISTOR PROCESS FOR MAKING ENHANCED GAIN LATERAL TRANSISTOR A process for producing simultaneously an NPN vertical bipolar transistor and a PNP lateral bipolar transistor on a recessed oxide-isolated epitaxial layer. An N+ buried layer is placed in the P- substrate beneath each transistor. P+ regions then are placed in the substrate underneath (or optionally in lieu of) the later formed recessed oxide and underneath the emitter region of each later formed lateral transistor. An N type epitaxial layer is deposited over the structure and the previously formed N+ and P+ substrate regions are outdiffused into the epitaxial layer, the P+ regions outdiffusing to a greater extent. Recessed oxide isolation walls are made and P+ areas are introduced into the epitaxial layer to form the base of each NPN transistor and to form a collector and an extended depth emitter for each PNP transistor, said emitter reaching from the surface of the epitaxial layer to the underlying N+ buried layer. The transistors are completed in the usual manner.

    METHOD FOR FORMING RECESSED DIELECTRIC ISOLATION WITH A MINIMIZED DBIRD'S BEAKD PROBLEM
    9.
    发明专利
    METHOD FOR FORMING RECESSED DIELECTRIC ISOLATION WITH A MINIMIZED DBIRD'S BEAKD PROBLEM 未知

    公开(公告)号：CA1043473A

    公开(公告)日：1978-11-28

    申请号：CA254112

    申请日：1976-06-04

    Applicant: IBM

    Inventor： ANTIPOV IGOR

    IPC: H01L21/76 ,  H01L21/00 ,  H01L21/762 ,  H01L21/94

    Abstract: A METHOD FOR FORMING RECESSED DIELECTRIC ISOLATION WITH A MINIMIZED "BIRD'S BEAK" PROBLEM In the fabrication of integrated circuits, a method is provided for forming recessed silicon dioxide isolation in integrated circuits in which the "bird's beak" problems associated with conventional silicon dioxide-silicon nitride composite masking structures is minimized. A conventional composite mask comprising a bottom layer of silicon dioxide and an upper layer of silicon nitride having a plurality of openings defining the regions in the silicon substrate which are to be thermally oxidized is formed on a silicon substrate. Recesses are then etched in the silicon substrate in registration with the openings in the composite mask. Then, the silicon dioxide layer is, in effect, over-etched to extend the openings in the silicon dioxide to greater lateral dimensions than the openings in the silicon nitride layer whereby the silicon nitride at the periphery of the openings is undercut. A layer of silicon is then deposited in the recesses covering the undercut portions of said silicon nitride layer. Then, the structure subjected to thermal oxidation whereby the silicon in and abutting the recesses is oxidized to form regions of recessed silicon dioxide substantially coplanar with the unrecessed portions of the silicon substrate. Because of the undercutting and the deposition of silicon in the recesses, the "bird's beak" effect is minimized.

    IGFET with improved props - using two stage doping in source and drain regions
    10.
    发明专利
    IGFET with improved props - using two stage doping in source and drain regions 未知

    公开(公告)号：FR2293795A1

    公开(公告)日：1976-07-02

    申请号：FR7533870

    申请日：1975-10-29

    Applicant: IBM

    Inventor： ANTIPOV IGOR ,  JADUS DALE K

    IPC: H01L29/78 ,  H01L21/8247 ,  H01L29/00 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  H01L21/38

    Abstract: Field effect transistors are made by (a) prepg. a semiconductor substrate of first conductivity type (b) forming a masking layer with a drain window (c) introducing an opposite type impurity into the exposed region through the window, (d) diffusing the impurity into the substrate and (e) introducing an additional impurity of second type conductivity into the opening to form a concentration of second type impyrities, important to the neighbourhood of the opening so that the drain region has a gradual changing impurity profile. Design of the device permits use of or max. working voltage for a given channel length.

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