METHOD AND MEANS FOR ADDRESSING A VERY LARGE MEMORY

    公开(公告)号:CA2075305C

    公开(公告)日:1998-09-29

    申请号:CA2075305

    申请日:1992-08-05

    Applicant: IBM

    Abstract: Provides relatively simple ways to obtain and control extenders (EXRs) for extending the size of small real and absolute addresses (up to 31 bit) to enable them to locate data or program entities anywhere in a very large memory (greater than 2**31). The EXR is concatenated to the high-order end of a conventionally-generated real or absolute address of less than 32 bit size to provide a real/absolute address of greater than 31 bit size (e.g. 63 bits). Each EXR value defines a section of a very large memory. The type of EXR location being used is indicated by having a CP extended address mode (CPEAM) field in a control register (CR). The CPEAM field indicates if the CP EXR field is associated with ARs, PTEs, STEs or ASTEs, or if a compatibility mode exists requiring no extender. When a CP program operates in the DAT-OFF mode, the EXR is contained in a register associated with a base register being currently used for operand address generation. When the CP is operating in DAT-ON mode, several different types of fields may be indicated, and the indicated EXR type is accessed during the address translation process, such when accessing an ASTEs, STE or PTE. The EXR field associated with the ASTE, STE or PTE is not used in the address translation process, but are only for address extension. By not affecting the translation process, the disclosure maintains downward compatibility for programs providing conventional small (e.g.31 bit) translated real addresses. Furthermore, an I/O EAM field is provided in a control block with each asynchronous I/O program to indicate the type of location being used for an I/O EXR field for providing the I/O EXR. The IOEAM field indicates if the I/O EXR field is associated with an ORB, CCWs, or IDAWs, or if a compatibility mode exists requiring no extender for I/O addressed data. This allows the I/O data of an I/O program to be mapped into one or plural sections of a very large memory, which may be the same or different from the section(s) addressed by the CP EXR.

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