公开(公告)号：CA2068796A1

公开(公告)日：1993-03-01

申请号：CA2068796

申请日：1992-05-15

Applicant: IBM

Inventor： CHOU NORMAN C ,  GUM PETER H ,  HOUGH ROGER E ,  KIM MOON J ,  MAZUROWSKI JAMES C ,  MCCAULEY DONALD W ,  SCALZI CASPER A ,  SCANLON JOHN F ,  WYMAN LESLIE W

IPC: G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F15/16

Abstract: P09-91-035 CPU EXPANSIVE GRADATION OF I/O INTERRUPTION SUBCLASS RECOGNITION A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.

公开(公告)号：CA2075305C

公开(公告)日：1998-09-29

申请号：CA2075305

申请日：1992-08-05

Applicant: IBM

Inventor： BAUM RICHARD I ,  CARLSON BRENT A ,  KIM MOON J ,  MALL MICHAEL G ,  SCALZI CASPER A ,  SINHA BHASKAR

IPC: G06F9/32 ,  G06F9/355 ,  G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  G06F13/16 ,  G06F15/16

Abstract: Provides relatively simple ways to obtain and control extenders (EXRs) for extending the size of small real and absolute addresses (up to 31 bit) to enable them to locate data or program entities anywhere in a very large memory (greater than 2**31). The EXR is concatenated to the high-order end of a conventionally-generated real or absolute address of less than 32 bit size to provide a real/absolute address of greater than 31 bit size (e.g. 63 bits). Each EXR value defines a section of a very large memory. The type of EXR location being used is indicated by having a CP extended address mode (CPEAM) field in a control register (CR). The CPEAM field indicates if the CP EXR field is associated with ARs, PTEs, STEs or ASTEs, or if a compatibility mode exists requiring no extender. When a CP program operates in the DAT-OFF mode, the EXR is contained in a register associated with a base register being currently used for operand address generation. When the CP is operating in DAT-ON mode, several different types of fields may be indicated, and the indicated EXR type is accessed during the address translation process, such when accessing an ASTEs, STE or PTE. The EXR field associated with the ASTE, STE or PTE is not used in the address translation process, but are only for address extension. By not affecting the translation process, the disclosure maintains downward compatibility for programs providing conventional small (e.g.31 bit) translated real addresses. Furthermore, an I/O EAM field is provided in a control block with each asynchronous I/O program to indicate the type of location being used for an I/O EXR field for providing the I/O EXR. The IOEAM field indicates if the I/O EXR field is associated with an ORB, CCWs, or IDAWs, or if a compatibility mode exists requiring no extender for I/O addressed data. This allows the I/O data of an I/O program to be mapped into one or plural sections of a very large memory, which may be the same or different from the section(s) addressed by the CP EXR.

公开(公告)号：CA2075305A1

公开(公告)日：1993-03-05

申请号：CA2075305

申请日：1992-08-05

Applicant: IBM

Inventor： BAUM RICHARD I ,  CARLSON BRENT A ,  KIM MOON J ,  MALL MICHAEL G ,  SCALZI CASPER A ,  SINHA BHASKAR

IPC: G06F9/32 ,  G06F9/355 ,  G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  G06F13/16 ,  G06F15/16