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    COEXECUTING METHOD AND MEANS FOR PERFORMING PARALLEL PROCESSING IN CONVENTIONAL TYPES OF DATA PROCESSING SYSTEMS
    2.
    发明专利
    COEXECUTING METHOD AND MEANS FOR PERFORMING PARALLEL PROCESSING IN CONVENTIONAL TYPES OF DATA PROCESSING SYSTEMS 未知

    公开(公告)号：CA2137488C

    公开(公告)日：1998-09-29

    申请号：CA2137488

    申请日：1994-12-07

    Applicant: IBM

    Inventor： BAUM RICHARD I ,  BRENT GLEN A ,  GHAFIR HATEM M ,  IYER BALAKRISHNA R ,  NARANG INDERPAL S ,  RAO GURURAJ S ,  SCALZI CASPER A ,  SHARMA SATYA P ,  SINHA BHASKAR ,  WILSON LEE H

    IPC: G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/50 ,  G06F15/16 ,  G06F15/177 ,  G06F9/28

    Abstract: A coexecutor for executing functions offloaded from central processors (CPs) in a data processing system, as requested by one or more executing control programs, which include a host operating system (host OS), and subsystem program s and applications executing under the host OS. The offloaded functions are embodied in code modules. Code modules execute in the coexecutor in parallel with non-offloaded functions being executed by the CPs. Thus, the CPs do not need to execute functions which can be executed by the coexecutor. CP requests to the coexecutor specify the code modules which are accessed by the coexecutor from host shared storage under the same constraints and access limitations as th e control programs. The coexecutor may emulate host dynamic address translation, and may use a provided host storage key in accessing host storage. The restricted access operating state for the coexecutor maintains data integrity. Coexecutors can be of the same architecture or of a totally different architecture from the CPs to provide an efficient processing environment for the offloaded functions. The coexecutor interfaces host software which provides the requests to the coexecutor. Offloaded modules, once accessed by the coexecutor, may be cached in coexecutor local storage for use by future requests to allow subsequent invocations to proceed without waiting to again load the same module.

    METHOD AND MEANS FOR ADDRESSING A VERY LARGE MEMORY
    3.
    发明专利
    METHOD AND MEANS FOR ADDRESSING A VERY LARGE MEMORY 未知

    公开(公告)号：CA2075305C

    公开(公告)日：1998-09-29

    申请号：CA2075305

    申请日：1992-08-05

    Applicant: IBM

    Inventor： BAUM RICHARD I ,  CARLSON BRENT A ,  KIM MOON J ,  MALL MICHAEL G ,  SCALZI CASPER A ,  SINHA BHASKAR

    IPC: G06F9/32 ,  G06F9/355 ,  G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  G06F13/16 ,  G06F15/16

    Abstract: Provides relatively simple ways to obtain and control extenders (EXRs) for extending the size of small real and absolute addresses (up to 31 bit) to enable them to locate data or program entities anywhere in a very large memory (greater than 2**31). The EXR is concatenated to the high-order end of a conventionally-generated real or absolute address of less than 32 bit size to provide a real/absolute address of greater than 31 bit size (e.g. 63 bits). Each EXR value defines a section of a very large memory. The type of EXR location being used is indicated by having a CP extended address mode (CPEAM) field in a control register (CR). The CPEAM field indicates if the CP EXR field is associated with ARs, PTEs, STEs or ASTEs, or if a compatibility mode exists requiring no extender. When a CP program operates in the DAT-OFF mode, the EXR is contained in a register associated with a base register being currently used for operand address generation. When the CP is operating in DAT-ON mode, several different types of fields may be indicated, and the indicated EXR type is accessed during the address translation process, such when accessing an ASTEs, STE or PTE. The EXR field associated with the ASTE, STE or PTE is not used in the address translation process, but are only for address extension. By not affecting the translation process, the disclosure maintains downward compatibility for programs providing conventional small (e.g.31 bit) translated real addresses. Furthermore, an I/O EAM field is provided in a control block with each asynchronous I/O program to indicate the type of location being used for an I/O EXR field for providing the I/O EXR. The IOEAM field indicates if the I/O EXR field is associated with an ORB, CCWs, or IDAWs, or if a compatibility mode exists requiring no extender for I/O addressed data. This allows the I/O data of an I/O program to be mapped into one or plural sections of a very large memory, which may be the same or different from the section(s) addressed by the CP EXR.

    NONHIERARCHICAL PROGRAM AUTHORIZATION MECHANISM
    6.
    发明专利
    NONHIERARCHICAL PROGRAM AUTHORIZATION MECHANISM 未知

    公开(公告)号：CA1313424C

    公开(公告)日：1993-02-02

    申请号：CA587711

    申请日：1989-01-06

    Applicant: IBM

    Inventor： BAUM RICHARD I ,  BORDEN TERRY L ,  BUTWELL JUSTIN R ,  CLARK CARL E ,  GANEK ALAN G ,  LUM JAMES ,  MALL MICHAEL G ,  PAGE DAVID R ,  PLAMBECK KENNETH E ,  SCALZI CASPER A ,  SCHMALZ RICHARD J

    IPC: G06F12/08 ,  G06F9/46 ,  G06F12/10 ,  G06F12/14 ,  G06F21/24

    Abstract: PO9-87-006 NONHIERARCHICAL PROGRAM AUTHORIZATION MECHANISM A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associated address space can only be accessed by an authorized program. For a program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.

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