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    PROCESS FOR FORMING EPITAXIALLY EXTENDED POLYCRYSTALLINE STRUCTURES
    3.
    发明专利
    PROCESS FOR FORMING EPITAXIALLY EXTENDED POLYCRYSTALLINE STRUCTURES 未知

    公开(公告)号：DE3176714D1

    公开(公告)日：1988-05-26

    申请号：DE3176714

    申请日：1981-10-27

    Applicant: IBM

    Inventor： DOO VEN YOUNG

    IPC: H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/768 ,  H01L29/04

    Abstract: Disclosed is a process for reducing microcracks (7) and microvoids (12) in the formation of polycrystalline (polysilicon) structures from initial layers (5) of amorphous silicon by annealing. In annealing of amorphous silicon (5) to the polycrystalline form, the crystal grains are thickness limited; and thus by maintaining the thickness below 100 nm, the spacing between contrasting material forming the crystal grains can be minimized on anneal. The resultant equiaxial grains are used as seed crystals for epi-like growth of silicon from them into the required or desired layerthickness.

    5.
    发明专利
    未知

    公开(公告)号：DE2253614A1

    公开(公告)日：1973-05-10

    申请号：DE2253614

    申请日：1972-11-02

    Applicant: IBM

    Inventor： DOO VEN YOUNG ,  HO IRVING TZE ,  JEN TEH-SEN

    IPC: G11C27/04 ,  G11C19/18 ,  H01L21/00 ,  H01L21/33 ,  H01L21/339 ,  H01L27/105 ,  H01L29/70 ,  H01L29/762 ,  G11C19/00

    Abstract: 1336301 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 17 Oct 1972 [3 Nov 1971] 47774/72 Heading H1K A capacitor structure forming part of a semiconductor device comprises a semi-conductor body, an insulating layer on a sufrace of the body, a layer of doped polycrystalline semiconductor material overlying the insulating layer, a second insulating layer on the layer of polycrystalline material and a layer of conductive material in ohmic contact with the semi-conductor body overlying the polycrystalline layer and separated therefrom by the second insulating layer, the semi-conductor body and conductive layer forming one electrode of the capacitor, the polycrystalline layer, the second electrode and the insulating layers the dielectric. As shown the device is a bucket brigade shift register wherein such capacitors are connected between the collector and base of an array of switching bipolar transistors (Figs. 1 and 2, not shown). The transistors, comprising collector 40, collector contact region 42, base 44 and emitter 46, are formed in epitaxial layer 36 on monocrystalline silicon substrate 34 after sub-collector diffusion 38 has been formed. The transistors are separated by isolation diffusions 48. Layer 36 is covered by insulating layer 50 comprising thermal SiO 2 or SiO 2 /Si 3 N 4 with apertures for emitter, base and collector contacts 16, 18, 14. Layer 52 of doped polycrystalline silicon is insulated from overlying conductive layer by thermal SiO 2 layer 54. The capacitance of the device is between extension (58) of collector terminal 14 (Fig. 3, not shown) and polycrystalline layer 52 and between. collector region 40 and layer 52, one layer being in electrical contact with base terminal 18 through opening (56) (Fig. 3, not shown) in layer 54. Preferably the base terminals extend alternatively in opposite directions to contactone of a pair of clock lines (Fig. 3, not shown), best illustrated by the prior art arrangement (Fig. 1, not shown). The various metal layers may be deposited aluminium. In an alternative construction the device uses field effect transistors (Figs. 4, 5, not shown).

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