公开(公告)号：JPS62106665A

公开(公告)日：1987-05-18

申请号：JP23024086

申请日：1986-09-30

Applicant: IBM

Inventor： SILVESTRI VICTOR JOSEPH ,  TSANG PAUL JAMIN

IPC: H01L27/082 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8228 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/73

公开(公告)号：DE3686310D1

公开(公告)日：1992-09-10

申请号：DE3686310

申请日：1986-10-23

Applicant: IBM

Inventor： SILVESTRI VICTOR JOSEPH ,  TSANG PAUL JAMIN

IPC: H01L27/082 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8228 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/73

Abstract: A method of fabricating dielectrically isolated integrated circuit devices, comprising the following steps: using a semiconductor substrate with upper and lower portions (14, 12), doping said upper portion (14) of said substrate in accordance with types of devices to be formed, said lower portion (12) of said substrate forming a plurality of subcollectors. (i)(a) forming a masking layer (20) over said substrate; (i)(b) etching a plurality of holes (30) in said masking layer; and (i)(c) isotropically etching a plurality of active device regions (40) in said substrate through said holes, (ii) growing an oxide layer (50) over portions of said substrate where said devices are to be formed; (iv) forming said devices by selective epitaxial growth in said regions (40).

公开(公告)号：DE3174815D1

公开(公告)日：1986-07-17

申请号：DE3174815

申请日：1981-10-20

Applicant: IBM

Inventor： SHEPARD JOSEPH FRANCIS ,  TSANG PAUL JAMIN

IPC: H01L27/10 ,  H01L21/28 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/532 ,  H01L27/108 ,  H01L29/78 ,  H01L23/52 ,  G11C11/24

公开(公告)号：DE3264103D1

公开(公告)日：1985-07-18

申请号：DE3264103

申请日：1982-02-10

Applicant: IBM

Inventor： DOO VEN YOUNG ,  TSANG PAUL JAMIN

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/336 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10 ,  H01L21/31 ,  H01L21/283

Abstract: A field effect transistor and method of making the same are disclosed. A thick mesa (17) of dielectric material is grown on a semiconductor substrate (10) and two or more layers (20a, b; 28a, b) of polycrystalline silicon grown on the vertical sides of the mesa (17) serve a masking function to define the gate region of the transistor with high accuracy. The mesa (17) and the two or more polycrystalline layers (20a, b; 28a, b) remain in the final device.

公开(公告)号：DE3686310T2

公开(公告)日：1993-03-18

申请号：DE3686310

申请日：1986-10-23

Applicant: IBM

Inventor： SILVESTRI VICTOR JOSEPH ,  TSANG PAUL JAMIN

IPC: H01L27/082 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8228 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/73

Abstract: A method of fabricating dielectrically isolated integrated circuit devices, comprising the following steps: using a semiconductor substrate with upper and lower portions (14, 12), doping said upper portion (14) of said substrate in accordance with types of devices to be formed, said lower portion (12) of said substrate forming a plurality of subcollectors. (i)(a) forming a masking layer (20) over said substrate; (i)(b) etching a plurality of holes (30) in said masking layer; and (i)(c) isotropically etching a plurality of active device regions (40) in said substrate through said holes, (ii) growing an oxide layer (50) over portions of said substrate where said devices are to be formed; (iv) forming said devices by selective epitaxial growth in said regions (40).

公开(公告)号：DE3466832D1

公开(公告)日：1987-11-19

申请号：DE3466832

申请日：1984-06-08

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  RISEMAN JACOB ,  TSANG PAUL JAMIN

IPC: H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L21/72 ,  H01L29/72 ,  H01L27/08

Abstract: The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region extending from the surface of the body to the buried N+ region acts as an electrical contact through the N+ buried layer to the base region. The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter formed around the periphery of a channel or groove which has at its base a insulating layer such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.