公开(公告)号：HK72485A

公开(公告)日：1985-10-04

申请号：HK72485

申请日：1985-09-26

Applicant: IBM

Inventor： BREWER JAMES A ,  EGGEBRECHT LEWIS C ,  KUMMER DAVID A ,  MCHUGH PATRICIA P

IPC: G06F12/02 ,  G11C11/406 ,  G11C7/00 ,  G06F12/16

Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a «D-type» latch (24) whose output, is turn, sets the highest priority DMA channel (0) request line (DREQO), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACKO) indicating the cycle is completed.

公开(公告)号：GB2103850A

公开(公告)日：1983-02-23

申请号：GB8222691

申请日：1982-08-06

Applicant: IBM

Inventor： BREWER JAMES A ,  EGGEBRECHT LEWIS C ,  MCHUGH PATRICIA P ,  KUMMER DAVID A

IPC: G06F12/02 ,  G11C11/406 ,  G11C7/00 ,  G06F13/00

Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a «D-type» latch (24) whose output, is turn, sets the highest priority DMA channel (0) request line (DREQO), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACKO) indicating the cycle is completed.

公开(公告)号：CA1184315A

公开(公告)日：1985-03-19

申请号：CA434110

申请日：1983-08-08

Applicant: IBM

Inventor： EGGEBRECHT LEWIS C ,  KUMMER DAVID A

IPC: G11C9/04

Abstract: : Extended Addressing Apparatus and Method For Direct Storage Access Devices A computing system storage addressing apparatus which extends the addressing capability of an address bus to enable direct storage (memory) storage access (DMA) channels to operate simultaneously in the same or different storage page. The computing system includes a processor, a plurality of storage devices, a data bus and an address bus interconnecting the processor and the storage devices, a DMA device controlling connection of a plurality of DMA channels to the address bus and data bus, a plurality of address register means for storing page address signals loaded from the processor, and gating means for gating to the address bus page address signals from an address register means corresponding to a currently active DMA channel.

公开(公告)号：GB2104757A

公开(公告)日：1983-03-09

申请号：GB8222695

申请日：1982-08-06

Applicant: IBM

Inventor： EGGEBRECHT LEWIS C ,  SAENZ JESUS A

IPC: G06F1/24 ,  G06F3/00 ,  G06F3/02 ,  G06F13/00 ,  H04L25/38 ,  H04L23/00

Abstract: A serial keyboard interface (28) connects a self scanning programmable serialized keyboard (40) to the system bus (10) of a data processing system. A cable (42) containing only a clock wire (52) and a data wire (58) provides the connection. The keyboard transmits a 9-bit scan out code consisting of a start bit followed by eight serial data bits. The keyboard clock line (52) is connected to the clock or shift terminal of a serial-to-parallel shift register encoder (62) for shifting the data bits on data line (58) into the encoder which has eight parallel output data lines (A, B . . . G, H) connected to the system bus. When the encoder (62) contains a complete scan out frame, the start bit is in the most significant stage (h') and sets the D-type latch (68) to apply a CPU interrupt request to the system bus (10). At this time, the &upbar& Q output of latch (68) pulls down the data line to ground potential, thereby disabling the data line and preventing further keyboard transmission of data. When the interrupt request is granted by the CPU, a clear signal resets latch (68) to remove ground potential from data line (58) and thereby permit further transmission of data.

公开(公告)号：GB2103850B

公开(公告)日：1985-03-20

申请号：GB8222691

申请日：1982-08-06

Applicant: IBM

Inventor： BREWER JAMES A ,  EGGEBRECHT LEWIS C ,  MCHUGH PATRICIA P ,  KUMMER DAVID A

IPC: G06F12/02 ,  G11C11/406 ,  G11C7/00 ,  G06F13/00

Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a «D-type» latch (24) whose output, is turn, sets the highest priority DMA channel (0) request line (DREQO), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACKO) indicating the cycle is completed.

公开(公告)号：CA1172386A

公开(公告)日：1984-08-07

申请号：CA403583

申请日：1982-05-21

Applicant: IBM

Inventor： EGGEBRECHT LEWIS C ,  KUMMER DAVID A ,  SAENZ JESUS A

IPC: G06F3/153 ,  G09G5/12 ,  G09G5/18 ,  G09G1/16

Abstract: SYNCHRONIZATION OF CRT CONTROLLER CHIPS Two controller units controlling a single input/ output device such as a cathode ray tube (CRT) are synchronized by a command signal. Upon appearance of the command signal, the slave controller unit, which may have been running unsynchronized with the master controller, is stopped at the time for vertical retrace and remains stopped until vertical retrace time for the master controller. At this point, the slave controller is restarted in synchronism with the master controller and remains synchronized so long as both master and slave receive the same clock and the same screen refresh parameters.