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    GAIN MEMORY CELL CIRCUIT
    3.
    发明专利
    GAIN MEMORY CELL CIRCUIT 失效

    公开(公告)号：JPH10241358A

    公开(公告)日：1998-09-11

    申请号：JP2699798

    申请日：1998-02-09

    Applicant: IBM

    Inventor： HOUGHTON RUSSELL J ,  BERTIN CLAUDE L ,  FIFIELD JOHN A ,  MILLER CHRISTOPHER P ,  TONTI WILLIAM R

    IPC: G11C11/402 ,  G11C11/403 ,  G11C11/405

    Abstract: PROBLEM TO BE SOLVED: To prevent read-out disturbance from an unselected cell by reading out a written word value stored on a storage node by means of a read transistor via a diode between bit lines. SOLUTION: When a write transistor Tw0 in a gain cell 20 is operated by a write-in word line WLW0, a value of a write-in bit line BLW0 is stored on the storage node SN0. When a read-out word line WLR0 is enabled to work, the read transistor Tr0 to be connected with the storage node SN0 in this case is connected via the diode D0 to a read-out bit line BLR0, so as to read out the stored value. The diode D0 is capable of preventing conductivity in the reverse direction of the read transistor Tr0, thus preventing disturbance from another cell, and also decreasing capacitance of the bit line. The same is the case with the other memory cells.

    ELECTRONICALLY PROGRAMMABLE ANTIFUSE AND CIRCUITS MADE THEREWITH
    4.
    发明申请
    ELECTRONICALLY PROGRAMMABLE ANTIFUSE AND CIRCUITS MADE THEREWITH 审中-公开
    电子可编程抗体和电路

    公开(公告)号：WO2005038869A3

    公开(公告)日：2006-02-09

    申请号：PCT/US2004032581

    申请日：2004-10-04

    Applicant: IBM ,  ABADEER WAGDI W ,  FIFIELD JOHN A ,  TONTI WILLIAM R

    Inventor： ABADEER WAGDI W ,  FIFIELD JOHN A ,  TONTI WILLIAM R

    IPC: H01L23/525 ,  H01L27/12 ,  H01L21/82 ,  H01L29/00

    CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit.

    Abstract translation: 一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。 当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。 当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。 反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。 该电压差非常高，可以使用简单的感测电路容易地感测。

    Stabilized direct sensing memory architecture
    6.
    发明专利
    Stabilized direct sensing memory architecture 有权
    稳定的直接感知存储器架构

    公开(公告)号：JP2003037491A

    公开(公告)日：2003-02-07

    申请号：JP2002136924

    申请日：2002-05-13

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： FIFIELD JOHN A ,  STORASKA DANIEL W ,  WIN K RUK

    IPC: H03K19/0175 ,  G11C7/06 ,  G11C11/409 ,  H03K19/0944

    CPC classification number: G11C7/04 ,  G11C7/067

    Abstract: PROBLEM TO BE SOLVED: To provide a stabilized direct sensing memory architecture which provides Process, Voltage and Temperature(PVT) compensation in a memory array to a direct sense circuit to increase the manufacturing yield thereof, and to extend the operating voltage and temperature ranges thereof independent of manufacturing tolerances. SOLUTION: A single-ended sense amplifier structure has a common source NFET amplifier with an adjustable current source load provided by a PFET. The PFET current source is automatically adjusted to place the NFET amplifier in an operating range to provide maximum amplification of a small signal, superimposed on a bitline precharge voltage. A simulating bias generator circuit provides this operating point adjustment, and realizes a direct, single-ended sensing operation using a small number of transistors.

    Abstract translation: 要解决的问题：提供一种稳定的直接感测存储器架构，其将存储器阵列中的过程，电压和温度（PVT）补偿提供给直接感测电路以增加其制造产量，并且延长其工作电压和温度范围 独立于制造公差。 解决方案：单端读出放大器结构具有公共源极NFET放大器，具有由PFET提供的可调电流源负载。 自动调节PFET电流源，使NFET放大器工作在一个工作范围内，以提供叠加在位线预充电电压上的小信号的最大放大。 模拟偏置发生器电路提供该工作点调整，并且使用少量晶体管实现直接的单端感测操作。

    Detection device for alpha particle or cosmic ray
    8.
    发明专利
    Detection device for alpha particle or cosmic ray 有权
    ALPHA颗粒或COSMIC RAY的检测装置

    公开(公告)号：JP2006024330A

    公开(公告)日：2006-01-26

    申请号：JP2004203670

    申请日：2004-07-09

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： FIFIELD JOHN A ,  KARTSCHOKE PAUL D ,  KLAASEN WILLIAM A ,  KOSONOCKY STEPHEN V ,  RANDY W MANN ,  OPPOLD JEFFERY H ,  ROHRER NORMAN J

    IPC: G11C11/41 ,  G01T1/17 ,  G11C29/04 ,  H01L21/8238 ,  H01L27/092

    Abstract: PROBLEM TO BE SOLVED: To provide a detection circuit and a method for detecting silicon well voltage or current indicating collision of an alpha particle or a cosmic ray to the silicon well in silicon substrate.
    SOLUTION: An effective application of the detection circuit is use in redundancy repair latches used for an SRAM. In the redundancy repair latches, normally writing is once performed when power is on in order to register wrong latch data, though writing is not performed again usually. When either state of these latches is altered by SER phenomena (soft error rate: collision of the alpha particle or the cosmic ray, and the like), the recovery data for the redundant latch of the SRAM is mapped incorrectly. In this detection circuit and the method, whether the SER phenomenon occurs in these latches is monitored, when occurring, reloading the recovery data is performed to the redundancy repair latches.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供检测电路和检测硅阱电压或电流的方法，所述硅阱电压或电流指示α粒子或宇宙射线与硅衬底中的硅阱的碰撞。

    解决方案：检测电路的有效应用是用于SRAM的冗余修复锁存器中。 在冗余修复锁存器中，通常只有在通电时才进行写入操作，才能注册错误的锁存器数据，但通常不会再写入。 当这些锁存器的任一状态被SER现象（软错误率：α粒子或宇宙射线的碰撞等）改变时，SRAM的冗余锁存器的恢复数据被映射不正确。 在该检测电路和方法中，监视这些锁存器中是否发生SER现象，发生时，对冗余修复锁存器进行恢复数据的重新加载。 版权所有（C）2006，JPO＆NCIPI

    Single bit-line direct sensing architecure for high-speed memory device
    9.
    发明专利
    Single bit-line direct sensing architecure for high-speed memory device 有权
    用于高速存储器件的单线直接感应架构

    公开(公告)号：JP2003030987A

    公开(公告)日：2003-01-31

    申请号：JP2002142731

    申请日：2002-05-17

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： FIFIELD JOHN A ,  STORASKA DANIEL W ,  WIN K RUK ,  STEPHENS JEREMY K ,  KIRIHATA TOSHIAKI

    IPC: G11C11/409 ,  G11C7/06 ,  G11C11/4091

    CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C11/4091

    Abstract: PROBLEM TO BE SOLVED: To provide a memory architecture, in which coupling noise between bit lines is small at CMOS intersection coupling sensing operation, and which operates at a high speed.
    SOLUTION: In a single bit-line direct sensing architecture, a sense amplifier circuit, having four transistors arranged for each memory array, is used. In this circuit, the transistor functions so that a data bit from a true bit-line of a pair of bit line or an auxiliary bit line is transferred selective to a data line. The data line is preferably arranged on a plurality of memory arrays, and the data line may not be required, to share in read operation and write operation. Furthermore, digital sensing scheme function is performed, by charging a data line during read-out operation using one more current source detecting the ratio of a current source, driving by a bit line of a corresponding array and resistance of a transistor.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：提供一种存储架构，其中位线之间的耦合噪声在CMOS交叉耦合感测操作处较小，并且以高速运行。 解决方案：在单个位线直接感测架构中，使用具有为每个存储器阵列布置的四个晶体管的读出放大器电路。 在该电路中，晶体管起作用，使得来自一对位线或辅助位线的真位置的数据位被选择性地传送到数据线。 数据线优选地布置在多个存储器阵列上，并且可能不需要数据线，以共享读操作和写操作。 此外，通过使用检测电流源的比例的一个电流源，通过相应阵列的位线驱动和晶体管的电阻来驱动读出操作期间的数据线，执行数字感测方案功能。

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