公开(公告)号：US3672948A

公开(公告)日：1972-06-27

申请号：US3672948D

申请日：1970-01-02

Applicant: IBM

Inventor： FOEHRING ROBERT A ,  GARNACHE RICHARD R ,  KENNEY DONALD M

IPC: C23C16/44 ,  C23C16/455 ,  C23C16/54 ,  C30B25/14 ,  C23C11/00 ,  C23C13/00

CPC classification number: C23C16/45504 ,  C23C16/455 ,  C23C16/45519 ,  C23C16/54 ,  C30B25/14 ,  Y10S148/006 ,  Y10S438/907 ,  Y10S438/935

Abstract: METHOD AND APPARATUS FOR CONTINUOUSLY CARRYING OUT MASS TRANSFER REACTIONS IN A REACTION CHAMBER UTILIZING LAMINAR FLOW TO PROVIDE DIFFUSION LIMITED TRANSPORT AND TO PROVIDE ISOLATION BETWEEN PROCESS STEPS. THERE IS PROVIDED A GASEOUS PHASE MATERIAL INLET FILTER TUBE TO INTRODUCE GASEOUS PHASE MATERIAL IN LAMINAR FLOW WITHIN A REACTION ZONE AND AN EXHAUST PRESSURE BAFFLE TO MAINTAIN LAMINAR FLOW THROUGHOUT THE REACTION ZONE. SUBSTRATES MAY BE CONTINUOUSLY PASSED THROUGH A REACTION ZONE TO PROVIDE AN INLINE SYSTEM.

公开(公告)号：US3645545A

公开(公告)日：1972-02-29

申请号：US3645545D

申请日：1970-07-30

Applicant: IBM

Inventor： GARNACHE RICHARD R ,  KENNY DONALD M

IPC: C30B31/10 ,  H01L21/677 ,  B65D53/00

CPC classification number: H01L21/67173 ,  C30B31/106 ,  Y10S277/906

Abstract: An atmospheric isolation device for separation of two atmospheres of a continuous semiconductor processing apparatus which includes a gas entry tube, a plurality of first gas restricting means leading to a first atmosphere, a plurality of second gas restricting means leading to a second atmosphere, and adjacent to each gas restricting means an expansion chamber for increasing back pressure and for destroying lift produced by the Bernouilli effect of the gas passing through the restricting means.

Abstract translation: 一种用于分离连续半导体处理装置的两个气氛的大气隔离装置，包括气体入口管，通向第一气氛的多个第一气体限制装置，通向第二气氛的多个第二气体限制装置，以及相邻的 每个气体限制装置是用于增加背压并破坏由通过限制装置的气体的伯努利效应产生的升力的膨胀室。

公开(公告)号：US3603284A

公开(公告)日：1971-09-07

申请号：US3603284D

申请日：1970-01-02

Applicant: IBM

Inventor： GARNACHE RICHARD R

IPC: C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C30B25/08 ,  C30B25/14 ,  C23C11/00

CPC classification number: C30B25/08 ,  C23C16/4588 ,  C30B25/14

Abstract: A vapor deposition reactor having a gaseous phase inlet and exit system including inlet means, located at one end of a reaction chamber, including a porous gas distribution baffle which forms a plenum and which uniformly delivers gaseous materials to substantially all of the horizontal cross-sectional area of the reaction chamber and further including an exit means, located at the other end of the chamber, comprising a porous pressure baffle for uniformly allowing the removal of gaseous materials from the chamber to prevent recirculation of reaction byproducts.

公开(公告)号：CA1159953A

公开(公告)日：1984-01-03

申请号：CA377171

申请日：1981-05-08

Applicant: IBM

Inventor： GARNACHE RICHARD R ,  KENNEY DONALD M ,  THOMA NANDOR G

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/423 ,  H01L29/78

Abstract: V-MOS Device with Self-Aligned Multiple Electrodes High density VMOSFET devices, particularly single transistor memory cells, are provided by use of series of simplified self-aligning process steps. Gate electrodes, source/drain regions and source/ drain contacts are provided with the aid of an initial mask-less photoresist removal process in which a relatively thick layer of self-leveling photoresist is uniformly removed in order to define portions of a gate electrode within the recess of a V-groove. The gate electrode subsequently acts as a self-aligned mask to define implanted source/ drain regions also within the V-groove and to enable second level interconnecting metallurgy contacts to be formed along the sidewalls of the V-groove. BU-978013

公开(公告)号：CA1283480C

公开(公告)日：1991-04-23

申请号：CA541434

申请日：1987-07-07

Applicant: IBM

Inventor： GARNACHE RICHARD R ,  KENNEY DONALD M

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

Abstract: Two Square Memory Cells A memory is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed on a given sidewall of the trench, switching means having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.

公开(公告)号：CA1166761A

公开(公告)日：1984-05-01

申请号：CA362828

申请日：1980-10-20

Applicant: IBM

Inventor： GARNACHE RICHARD R ,  KENNEY DONALD M

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/336

Abstract: METHOD FOR PROVIDING SELF-ALIGNED: CONDUCTOR IN A V GROOVE DEVICE A method for providing self-aligned conductors in vertically integrated semiconductor devices which includes providing recesses in the surface of a semiconductor substrate for the fabrication of Vgroove devices, providing a conductive layer over the surface and then applying a layer of masking material over the conductive layer to form a planar upper surface, selectively etching the masking material until it remains only in the recesses and then selectively etching the exposed portion of the conductive layer. BU-9-78-012

公开(公告)号：CA997482A

公开(公告)日：1976-09-21

申请号：CA187388

申请日：1973-12-05

Applicant: IBM

Inventor： GARNACHE RICHARD R ,  SMITH WILLIAM M JR

IPC: G11C11/41 ,  H01L21/225 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/07 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

Abstract: Integrated circuits of high density are fabricated in a simplified process which allows both the use of multiple conducting layers in a dielectric above a semiconductor substrate, such as a polycrystalline silicon (polysilicon) field shield and metal interconnection lines, while also making provision for very precise alignment of subsequent layers to diffusions. A doped oxide containing a suitable dopant, such as arsenic in the case of a p-type silicon substrate, is deposited on the substrate. A pattern corresponding to desired diffusions is generated by normal photolithographic and etching techniques. A second, undoped oxide layer is thermally grown over the semiconductor substrate with dopant from the doped oxide simultaneously diffusing into areas of the substrate underlying the doped oxide. The undoped oxide serves to prevent autodoping. Thermally growing the undoped oxide layer converts a layer of the semiconductor surface not covered by doped oxide to the undoped oxide. Both oxide layers are then removed, leaving slight steps at the surface of the semiconductor substrate around the diffusion. The slight steps serve to allow very precise alignment of masks for subsequent process steps. Otherwise, the structure produced is very planar. An insulating layer, desirably a composite of silicon dioxide and silicon nitride in the case of a silicon substrate, is then formed on the substrate, followed by a layer of polycrystalline semiconductor, desirably doped to provide high conductivity. Openings are then etched in the polycrystalline semiconductor layer to allow formation of gate electrodes of FET's, contact to the substrate, and contact of a subsequent interconnection metallization to diffusions in some of the circuits. A second insulating layer, such as silicon dioxide, is then grown on the polycrystalline semiconductor layer. Contact holes are then made to diffusions in the substrate, the substrate itself, and the polycrystalline silicon. The deposition and etching of an interconnection layer on the second insulating layer completes fabrication of the integrated circuit.