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    Resistance standard
    2.
    发明授权
    Resistance standard 失效
    电阻标准

    公开(公告)号：US3609537A

    公开(公告)日：1971-09-28

    申请号：US3609537D

    申请日：1969-04-01

    Applicant: IBM

    Inventor： HEALY ALBERT M ,  KENNEY DONALD M

    IPC: G01N27/04 ,  G01R25/00 ,  G01R27/14 ,  G01R1/02

    CPC classification number: G01N27/041 ,  G01R25/00

    Abstract: A resistance standard for calibrating four-point probes used to measure resistances of semiconductor material has a metal pattern having an area of known resistance value deposited on the surface of a semiconductor wafer. Four diffused areas of opposite conductivity to the remainder of the wafer are disposed adjacent to and are electrically connected to the area of known resistance value. One point of the probe is contacted to each of the diffused areas to connect the probe to the standard. A constant current is passed through the area of known resistance and the voltage drop across the area measured. This standard is both stable and allows probe to semiconductor contact experienced in actual measurements to be duplicated during calibration of the probe.

    3.
    发明专利
    未知

    公开(公告)号：ES2072930T3

    公开(公告)日：1995-08-01

    申请号：ES90102773

    申请日：1990-02-13

    Applicant: IBM

    Inventor： KENNEY DONALD M

    IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

    Abstract: A very small memory cell utilizing only two squares at a major surface is provided which includes a semiconductor substrate (26) having a major surface and a trench (24) disposed therein having a longitudinal axis, a storage capacitor (16) having a storage node (20) disposed within a given sidewall of the trench (24), a switching device (12) coupled to the storage capacitor (16) and having an elongated current carrying element (22) disposed within the given sidewall with its longitudinal direction arranged parallel to that of the longitudinal axis of the trench (24) and a control element (14) disposed on the sidewall of the trench (24) between the storage capacitor (16) and the elongated current carrying element (22), and an electrically conductive line (28) disposed on the major surface of the semiconductor substrate (26) in a direction orthogonal to the longitudinal axis of the trench (24) and in contact with the control element (14) of the switching device (12). Furthermore, two complete memory cells (10A, 10B) are formed at each trench-word line intersection with one cell formed on each side of the trench (24) at each intersection.

    5.
    发明专利
    未知

    公开(公告)号：DE69019414T2

    公开(公告)日：1996-01-25

    申请号：DE69019414

    申请日：1990-02-13

    Applicant: IBM

    Inventor： KENNEY DONALD M

    IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

    Abstract: A very small memory cell utilizing only two squares at a major surface is provided which includes a semiconductor substrate (26) having a major surface and a trench (24) disposed therein having a longitudinal axis, a storage capacitor (16) having a storage node (20) disposed within a given sidewall of the trench (24), a switching device (12) coupled to the storage capacitor (16) and having an elongated current carrying element (22) disposed within the given sidewall with its longitudinal direction arranged parallel to that of the longitudinal axis of the trench (24) and a control element (14) disposed on the sidewall of the trench (24) between the storage capacitor (16) and the elongated current carrying element (22), and an electrically conductive line (28) disposed on the major surface of the semiconductor substrate (26) in a direction orthogonal to the longitudinal axis of the trench (24) and in contact with the control element (14) of the switching device (12). Furthermore, two complete memory cells (10A, 10B) are formed at each trench-word line intersection with one cell formed on each side of the trench (24) at each intersection.

    TWO SQUARE MEMORY CELLS
    7.
    发明专利
    TWO SQUARE MEMORY CELLS 未知

    公开(公告)号：CA1283480C

    公开(公告)日：1991-04-23

    申请号：CA541434

    申请日：1987-07-07

    Applicant: IBM

    Inventor： GARNACHE RICHARD R ,  KENNEY DONALD M

    IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

    Abstract: Two Square Memory Cells A memory is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed on a given sidewall of the trench, switching means having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.

    TWO SQUARE MEMORY CELLS HAVING HIGHLY CONDUCTIVE WORD LINES
    8.
    发明专利
    TWO SQUARE MEMORY CELLS HAVING HIGHLY CONDUCTIVE WORD LINES 未知

    公开(公告)号：CA1321834C

    公开(公告)日：1993-08-31

    申请号：CA613499

    申请日：1989-09-27

    Applicant: IBM

    Inventor： KENNEY DONALD M

    IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/24

    Abstract: A very small memory cell utilizing only two squares at a major surface is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, a storage capacitor having a storage node disposed within a given sidewall of the trench, a switching device coupled to the storage capacitor and having an elongated current carrying element disposed within the given sidewall with its longitudinal direction arranged parallel to that of the longitudinal axis of the trench and a control element disposed on the sidewall of the trench between the storage capacitor and the elongated current carrying element, and an electrically conductive line disposed on the major surface of the semiconductor substrate in a direction orthogonal to the longitudinal axis of the trench and in contact with the control element of the switching device. Furthermore, two complete memory cells are formed at each trench-word line intersection with one cell formed on each side of the trench at each intersection.

    PROCESS FOR MAKING COMPLEMENTARY TRANSISTORS
    9.
    发明专利
    PROCESS FOR MAKING COMPLEMENTARY TRANSISTORS 未知

    公开(公告)号：CA1191973A

    公开(公告)日：1985-08-13

    申请号：CA440689

    申请日：1983-11-08

    Applicant: IBM

    Inventor： COTTRELL PETER E ,  GEIPEL HENRY J JR ,  KENNEY DONALD M

    IPC: H01L27/08 ,  H01L21/00 ,  H01L21/76 ,  H01L21/762 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02

    Abstract: ABS Process for Making Complementary Transistors A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.

    DENSE DYNAMIC MEMORY CELL STRUCTURE AND PROCESS
    10.
    发明专利
    DENSE DYNAMIC MEMORY CELL STRUCTURE AND PROCESS 未知

    公开(公告)号：CA1183954A

    公开(公告)日：1985-03-12

    申请号：CA403562

    申请日：1982-05-21

    Applicant: IBM

    Inventor： KENNEY DONALD M

    IPC: H01L27/10 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/535 ,  H01L27/108 ,  H01L29/78 ,  G11C11/34

    Abstract: Dense Dynamic Memory Cell Structure and Process A dynamic memory is provided having a cell with an improved structure and made by an improved process which substantially reduces the capacitance of the bit/sense line connected to the cell. The cell has one field effect transistor and a storage node, and the cell structure includes a thick insulating segment located under a portion of a conductive layer or field shield and under a portion of the gate electrode of the transistor, while extending over the entire diffusion region of the bit/sense line and over substantially the entire depletion region surrounding the bit/sense line diffusion region.

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