Patent search ap:("IBM") AND inv:"HALLER WILHELM E" Page 1

1.

发明专利
未知

公开(公告)号：DE10225862B4

公开(公告)日：2009-12-17

申请号：DE10225862

申请日：2002-06-11

Applicant: IBM DEUTSCHLAND

Inventor： HALLER WILHELM E , SAUTTER ROLF , WENDEL DIETER , WETTER HOLGER

IPC: G06F7/50 , G06F7/506 , G06F7/507 , G06F9/30

2.

发明专利
Computer hardware logic circuit for testing address regions is configured to implement Boolean logic equations that have a reduced chip space requirement 未知

公开(公告)号：DE10213352A1

公开(公告)日：2003-01-16

申请号：DE10213352

申请日：2002-03-26

Applicant: IBM

Inventor： HALLER WILHELM E , KESSLER FRIEDHELM , NISSLER DIETER , WOERNER ALEXANDER

IPC: G06F7/02 , G06F9/30 , G06F9/34 , G06F9/312 , G06F9/315

Abstract: Method for testing of two multiple bit numbers for determining whether one of two conditions is fulfilled, either A + 1 equals B or A equals B, whereby the method avoids a remainder carry over by use of a comparison of a remainder value for each of the i bit positions of a number. The invention also relates to a corresponding hardware logic circuit.

3.

发明专利
Active window management system for operation of a data buffer provides automatic operation using tags 未知

公开(公告)号：DE10118065A1

公开(公告)日：2001-10-25

申请号：DE10118065

申请日：2001-04-11

Applicant: IBM

Inventor： HALLER WILHELM E , LEENSTRA JENS , SAUTTER ROLF , WENDEL DIETER , WERNICKE FRIEDRICH-CHRISTIAN

IPC: G06F9/38 , G06F12/08

Abstract: The entry of data into a buffer memory (10) is made using three sets of status information (20,22,24) that are specific to processes. The status information is evaluated by combinational logic, an input pointer and an output pointer

4.

发明专利
未知

公开(公告)号：DE10213352B4

公开(公告)日：2004-11-11

申请号：DE10213352

申请日：2002-03-26

Applicant: IBM

Inventor： HALLER WILHELM E , KESSLER FRIEDHELM , NISSLER DIETER , WOERNER ALEXANDER

IPC: G06F7/02 , G06F9/30 , G06F9/34 , G06F9/312 , G06F9/315

5.

发明专利
Transfer network for addition of two bit groups such that circuit performance is enhanced and adding speed improved by use of a redundant logic circuit solely comprising NAND gates and inverters 未知

公开(公告)号：DE10225862A1

公开(公告)日：2003-01-30

申请号：DE10225862

申请日：2002-06-11

Applicant: IBM DEUTSCHLAND

Inventor： HALLER WILHELM E , SAUTTER ROLF , WENDEL DIETER , WETTER HOLGER

IPC: G06F7/506 , G06F7/507 , G06F9/30

Abstract: Method for generating a transfer signal (cy) from a transfer network (2) that is for adding two bit groups together (A, B) in an adder circuit, whereby the transfer network is implemented as a static hardware circuit. The circuit is based on a redundant logic circuit comprised solely of NAND gates (AI) and inverters (I). A further transfer path does not have inverters.

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