公开(公告)号：DE3163966D1

公开(公告)日：1984-07-12

申请号：DE3163966

申请日：1981-06-10

Applicant: IBM

Inventor： CHANG KENNETH ,  CHIU GEORGE TEIN-CHU ,  HOEG ANTHONY JOHN ,  LEE LINDA HWA-CHUN

IPC: H01L21/3213 ,  G03F7/00 ,  H05K3/00 ,  H05K3/06 ,  H05K3/10 ,  H05K3/14 ,  H05K3/16 ,  H05K3/46 ,  G03F7/26 ,  H01L23/50

Abstract: In the process a first and a second layer (12 or 14 respectively) of insulative material, first layer (12) being etchable selectively in the presence of second layer (14) and a photoresist layer (16), are deposited successively. A pattern corresponding to the negative of the desires metallurgy pattern is formed photolithographically followed by the etching of the areas of layers (12) and (14) not covered by the photoresist. Then a blanket metal layer (24) is deposited. Thereon a planarizing photoresist layer (26, 28) is applied and subsequently etched to expose high spots (32) of metal layer (24), and finally metal high spots (32) are etched to a depth sufficient to expose the surface of second layer (14). … The process is useful in forming planar single- or multilevel metal interconnection systems for integrated circuits with high component density.

公开(公告)号：DE3379132D1

公开(公告)日：1989-03-09

申请号：DE3379132

申请日：1983-12-01

Applicant: IBM

Inventor： HOEG ANTHONY JOHN ,  KROLL CHARLES THOMAS ,  STEPHENS GEOFFREY BROWNELL

IPC: H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28 ,  H01L29/60

Abstract: A process for placing non-continuous Dual Electron Injection Structures (DEIS) between two layers of polysilicon used to form an array of poly devices on an integrated circuit substrate. Separate masks are used to define Poly 1 and Poly 2 devices, respectively. The DEIS structure is disposed above the poly 1 devices. A silicon nitride (Si 3 N 4 ) layer is used to mask the DEIS structure and prevents it from oxidizing during certain processing steps. A thin layer of poly x is placed between the DEIS structure and the Si 3 N 4 . The poly x layer forms a buffer and protects the DEIS during an etching step which removes the Si 3 N 4 layer.