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    3.
    发明专利
    未知

    公开(公告)号：DE3671329D1

    公开(公告)日：1990-06-21

    申请号：DE3671329

    申请日：1986-02-05

    Applicant: IBM

    Inventor： KROLL JR ,  STEPHENS GEOFFREY BROWNELL

    IPC: H01L21/8247 ,  G11C17/00 ,  H01L21/314 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/62 ,  H01L29/60 ,  H01L21/28 ,  H01L29/78

    Abstract: @ A dual electron injection structure (DEIS) and process for incorporating it into a semi-conductor structure, such as an EEPROM and/or NVRAM, is disclosed. The DEIS includes a composite structure formed from a layer of silicon rich nitride (5'), a layer of silicon dioxide (7) and a layer of silicon rich oxide (9). Preferably, a Plasma Enhanced Chemical Vapor Deposit (PECVD) method or a low pressure chemical vapor deposit (LPCVD) method is used to place the DEIS between the Poly 1 (3) and Poly 2 (13; 15) devices of the semi-conductor structure.

    ON CHIP CHARGE TRAP COMPENSATED HIGH VOLTAGE CONVERTER
    4.
    发明专利
    ON CHIP CHARGE TRAP COMPENSATED HIGH VOLTAGE CONVERTER 未知

    公开(公告)号：DE3479362D1

    公开(公告)日：1989-09-14

    申请号：DE3479362

    申请日：1984-03-05

    Applicant: IBM

    Inventor： HOFFMAN CHARLES REEVES ,  STEPHENS GEOFFREY BROWNELL

    IPC: H01L27/06 ,  G11C5/14 ,  G11C16/06 ,  G11C17/00 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L29/788 ,  H01L29/792 ,  H02M3/07 ,  G11C5/00 ,  H02M3/06 ,  H02M7/10

    Abstract: The invention is an improved on chip low voltage to high voltage converter. A capacitive charge pump circuit driven by an asynchronous inverter is used. The charge pump has improved voltage regulation that automatically compensates for process variation in the required program/ erase voltage and for charge trapping in the oxide layer of electrically alterable memory products. A charge trapping material that tracks the charge trapping occurring in memory products is used in a feedback circuit to control the output voltage supply. As charge trapping occurs, the output supply voltage is boosted. This overcomes the effects of charge trapping and provides increased cycles of writing and erasing for a semiconductor memory that suffers from charge trapping in its oxide insulation. A dual electron injector structure is used to monitor the charge trapping effect. A typical one order magnitude increase in the number of write or erase cycles before memory degradation occurs can be achieved with this invention.

    PROCESS FOR MANUFACTURING A TWICE DIFFUSED LATERAL TRANSISTOR AND A COMPLEMTARY VERTICAL TRANSISTOR INTEGRATED THEREWITH
    5.
    发明专利
    PROCESS FOR MANUFACTURING A TWICE DIFFUSED LATERAL TRANSISTOR AND A COMPLEMTARY VERTICAL TRANSISTOR INTEGRATED THEREWITH 未知

    公开(公告)号：DE2862475D1

    公开(公告)日：1986-01-09

    申请号：DE2862475

    申请日：1978-08-16

    Applicant: IBM

    Inventor： BERGERON DAVID LEO ,  PUTNEY ZIMRI CONGDON ,  STEPHENS GEOFFREY BROWNELL

    IPC: H01L21/033 ,  H01L21/31 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8226 ,  H01L27/082 ,  H01L29/06 ,  H01L29/08 ,  H01L29/73 ,  H01L21/265

    Abstract: An improved merged transistor logic (I2L) process is disclosed which provides a practical technique for forming micron to sub-micron window size devices. In a single step, the process forms all of the contact and guard ring windows in the passivation layer and then by use of selective blocking of various combinations of these windows, the various ion-implanted regions of the devices are formed with a minimum number of hot processing steps. A second embodiment of the method forms a double diffused lateral PNP device having an asymmetrically placed emitter within the base so as to enhance the injection efficiency in the vicinity of the collector. A micron to sub-micron window for the formation of all contacts and guard ring permits a merged transistor logic structure to be formed having a reduced upward NPN collector-base capacitance, lower PNP emitter-base diffusion capacitance, a lower PNP base series resistance, and an increased probability of avoiding collector-emitter pipe defects. The formation of all the windows in the passivation layer and the use of selective photoresist blocking to define the various ion-implanted regions in the device permit the practical formation of a minimum size (self-aligned contact to guard ring) MTL device with a minimum number of critical mask and hot processing steps. The advantages also apply to downward NPN and individual PNP devices.

    PROCESS FOR MANUFACTURING INTEGRATED IMPLANTED LOGIC CIRCUITS WITH A HARDENED PHOTORESIST MASK
    6.
    发明专利
    PROCESS FOR MANUFACTURING INTEGRATED IMPLANTED LOGIC CIRCUITS WITH A HARDENED PHOTORESIST MASK 未知

    公开(公告)号：DE2961204D1

    公开(公告)日：1982-01-14

    申请号：DE2961204

    申请日：1979-03-29

    Applicant: IBM

    Inventor： ALCORN GEORGE EDWARD ,  BERGERON DAVID LEO ,  STEPHENS GEOFFREY BROWNELL

    IPC: H01L29/73 ,  H01L21/027 ,  H01L21/266 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/331 ,  H01L21/8226 ,  H01L21/31 ,  H01L21/265

    Abstract: An improved mask fabrication process is disclosed which may be broadly applied to ion-implantation, reactive plasma etching, or the etching of semiconductor structures. The process is based upon the deposition onto an oxide coated or bare semiconductor surface, of a first photoresist layer having formed therein a plurality of windows and which is hardened by a wet chemical technique so as to have an increased resistance to dissolution in solvents. A second photoresist layer is deposited over the surface and windows of the first layer and a subplurality of windows are formed therein over selected windows in the first photoresist layer so as to selectively block a portion of the plurality of windows in the first layer. This composite mask invention may then be employed to carry out an ion-implantation step, wet etching step or reactive plasma etching step on the oxide or semiconductor surface exposed through composite windows. The second layer of photoresist may then be removed and a substitute photoresist layer may be deposited on the surface and windows of the first, hardened photoresist layer and a different subplurality of windows in the substitute layer may be selectively formed over selected windows in the hardened photoresist layer, thereby selectively blocking a different combination of windows in the first, hardened layer.

    ELECTRICALLY ALTERABLE READ ONLY MEMORY CELL
    8.
    发明专利
    ELECTRICALLY ALTERABLE READ ONLY MEMORY CELL 未知

    公开(公告)号：DE3176416D1

    公开(公告)日：1987-10-08

    申请号：DE3176416

    申请日：1981-05-19

    Applicant: IBM

    Inventor： CRANFORD HAYDEN CLAVIE ,  HOFFMAN CHARLES REEVES ,  STEPHENS GEOFFREY BROWNELL

    IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L27/10 ,  H01L29/60

    Abstract: In the electrically alterable read only memory cell a reduction in cell area and an improvement in tolerance allowed for programming and erase voltages is achieved utilizing a diffused control gate (3) having improved capacitive coupling to the floating gate (7) through a thin oxide layer (5) grown on single crystal silicon (1). A thin oxide layer (6) is also grown over the channel area (2). Polyoxide layers (8) and (10) isolate the programming gate (9) from the floating gate (7) and the latter from the erase gate (11). The ratio of thickness between the oxide layers (5) and (6) and the polyoxide layers (8) and (10) is of one to four or five.

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