公开(公告)号：DE3379132D1

公开(公告)日：1989-03-09

申请号：DE3379132

申请日：1983-12-01

Applicant: IBM

Inventor： HOEG ANTHONY JOHN ,  KROLL CHARLES THOMAS ,  STEPHENS GEOFFREY BROWNELL

IPC: H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28 ,  H01L29/60

Abstract: A process for placing non-continuous Dual Electron Injection Structures (DEIS) between two layers of polysilicon used to form an array of poly devices on an integrated circuit substrate. Separate masks are used to define Poly 1 and Poly 2 devices, respectively. The DEIS structure is disposed above the poly 1 devices. A silicon nitride (Si 3 N 4 ) layer is used to mask the DEIS structure and prevents it from oxidizing during certain processing steps. A thin layer of poly x is placed between the DEIS structure and the Si 3 N 4 . The poly x layer forms a buffer and protects the DEIS during an etching step which removes the Si 3 N 4 layer.

公开(公告)号：DE3276733D1

公开(公告)日：1987-08-13

申请号：DE3276733

申请日：1982-04-15

Applicant: IBM

Inventor： FARRAR PAUL ALDEN ,  GEFFKEN ROBERT MICHAEL ,  KROLL CHARLES THOMAS

IPC: H01L23/522 ,  H01L21/027 ,  H01L21/28 ,  H01L21/768 ,  H01L21/90

Abstract: A method for providing high density multiple level metallurgy for integrated circuit devices in which a relatively thin layer of plasma produced silicon nitride (24) is deposited over a first level of interconnection metallurgy (22) formed on a layer of silicon oxide. Overlap via holes are etched in the nitride layer followed by deposition of a thicker layer of polyimide forming polymer (28). A second set of via holes (29) larger than the first are provided in the polymer layer (28) and a second layer of interconnection metallurgy (30) is then deposited by a lift-off deposition technique.

公开(公告)号：DE2646300A1

公开(公告)日：1977-05-05

申请号：DE2646300

申请日：1976-10-14

Applicant: IBM

Inventor： KEENAN WILLIAM ANDREW ,  KROLL CHARLES THOMAS

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/318 ,  H01L21/425 ,  H01L21/471

Abstract: The disclosure teaches the use of aluminum nitride as a mask for utilization of ion implantation in the formation of semiconductor configurations as well as an underlying material for use in semiconductor lift-off techniques in device formation and the deposition of metallization contact lines and interconnections.

公开(公告)号：DE2627827A1

公开(公告)日：1977-01-27

申请号：DE2627827

申请日：1976-06-22

Applicant: IBM

Inventor： BHATTACHARYYA ARUP ,  JOSHI MADHUKAR LAXMAN ,  KROLL CHARLES THOMAS ,  SILVERMAN DONALD

IPC: H01L27/112 ,  G11C17/00 ,  G11C17/08 ,  H01L21/3105 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/088 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/08

Abstract: Fully integrated non-volatile and fixed threshold field effect devices are fabricated in N-channel technology on a single semiconductor substrate. MOSFET devices of the metal-nitride-oxide-semiconductor (MNOS) devices are used both as fixed threshold support devices and as variable threshold non-volatile memory array devices. Extremely stable and reproducible device characteristics result from the use of low charge containing dielectrics which allow optimum variable threshold stability and allow the use of operating potentials compatable with conventional fixed threshold FET devices. Low temperature processing following deposition of variable threshold gate dielectric enables all enhancement mode operation. A field oxide structure including a thin silicon dioxide layer, an aluminum oxide layer and a nitride layer provides parasitic threshold voltages in excess of 60 volts and prevents sub-threshold leakage.