LOGIC CIRCUIT
    1.
    发明专利

    公开(公告)号:DE3367472D1

    公开(公告)日:1986-12-11

    申请号:DE3367472

    申请日:1983-04-20

    Applicant: IBM

    Abstract: A logic carry circuit for carries involved in the addition of two binary numbers A3 A2 A1 A0 and B3 B2 B1 B0 comprises AND gate 1, exclusive OR gate 9, transfer FET gate 14 connected to a carry-in line Cin, an inverter 19, an FET 18 connected to ground, and an OR gate 5, the carry output for digits A0 and B0 being C0, and the circuit being extended to the left and down for other digit pairs as shown. If A0 and B0 = "1", C0 = "1" due to AND gate 1 and OR gate 5, and line 20 immediately to the left of FET 14 is grounded by FET 18 due to exclusive OR 9. If only one of A0 and B0 = "1", and Cin = "1", Cin is transferred via FET 14 to OR gate 5, which produces C0 = "1". In the latter case if Cin had equalled "0", C0 would equal "0". The remainder of the circuit operates similarly.

    2.
    发明专利
    未知

    公开(公告)号:DE3485193D1

    公开(公告)日:1991-11-28

    申请号:DE3485193

    申请日:1984-06-08

    Applicant: IBM

    Abstract: A digital shifter/rotator (1000) for shifting an input word by an amount depending on a shift control word (4000) is described. The shifter/rotator comprises an array of FET pass transistors arranged in a sequential number of stages (1200, 1400, 1600, 1700, 1800). The amount to be shifted in each stage is controlled by a corresponding shift control bit on lines 4200 of the shift control word buffered by drivers 4500, whereby the output word of the rotator is the input word shifted by an amount equal to a sum of the number of shifts effected in each of the stages as determined by the shift control word. The rotator features selectable amount of shift in one machine cycle, high performance and reduced device count. Further improved performance is obtained by utilizing decoupling devices for isolating the input points of the stages, except when providing rotation, from the long rotation cross buses and its associated large parasiticcapac- itances.

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