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    2.
    发明专利
    未知

    公开(公告)号：DE3867964D1

    公开(公告)日：1992-03-05

    申请号：DE3867964

    申请日：1988-07-05

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  CHAPPELL TERRY IVAN ,  SCHUSTER STANLEY EVERETT

    IPC: G11C11/41 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/401 ,  G11C11/413 ,  G11C8/00 ,  G11C7/00

    Abstract: A semiconductor random access memory chip wherein the cycle time is less than the access time for any combination of read or write sequence. The semiconductor random access memory chip is partitioned into relatively small sub-arrays with local decoding (RS, WS) and precharging (BLPC). The memory chip operates in a pipelined manner with more than one access propagating through the chip at any given time and wherein the cycle time is limited by sub-array cycles wherein the cycle time is less than the access time for a memory chip having cycle times greater than access times for accesses through the same sub-array. The memory chip also incorporates dynamic storage techniques for achieving very fast access and precharge times.

    4.
    发明专利
    未知

    公开(公告)号：BR8901970A

    公开(公告)日：1989-12-05

    申请号：BR8901970

    申请日：1989-04-26

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  LIEN YEONG-CHANG ,  TANG JEFFREY YUH-FONG

    IPC: G11C11/41 ,  G11C8/12 ,  G11C5/02

    Abstract: A transposable memory architecture for providing equally fast access to stored data in two or more dimensions. This architecture is provided by orthogonal wiring of access devices, word lines and bit lines with independent random accessing capability for data in each direction. The transposable memory architecture (TMA) cell directly implements the TMA architecture using only one access device per dimension of access. This invention also describes multiple transposable memory architecture (MTMA) device for additional data path flexibility. The read and write operations described provide access and cycle times approximately equivalent to those for a convention one-dimension RAM.

    INTERMEDIATE STRUCTURE FOR USE IN THE MANUFACTURE OF SEMICONDUCTOR DEVICES, METHOD OF MAKING FIELD EFFECT TRANSISTORS AND TRANSISTORS
    5.
    发明专利
    INTERMEDIATE STRUCTURE FOR USE IN THE MANUFACTURE OF SEMICONDUCTOR DEVICES, METHOD OF MAKING FIELD EFFECT TRANSISTORS AND TRANSISTORS 未知

    公开(公告)号：DE3278605D1

    公开(公告)日：1988-07-07

    申请号：DE3278605

    申请日：1982-10-14

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  CHAPPELL TERRY IVAN ,  WOODALL JERRY MCPHERSON

    IPC: H01L29/80 ,  H01L21/3063 ,  H01L21/331 ,  H01L21/338 ,  H01L27/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/267 ,  H01L29/73 ,  H01L29/812 ,  H01L29/861 ,  H01L29/72

    Abstract: An intermediate structure for use in the manufacture of semiconductor devices such as field effect transistors, comprises a monocrystalline semiconductor body having a first outer layer (2), a central layer (3) and a second outer layer (4) each of said first and second outer layers being of semiconductor material different from the semiconductor material of the central layer and forming a heterojunction (5, 6) whith the central layer. The thickness of the central layer (3) is of the order of the transport length of a charge carrier in the semiconductor material of that layer. Preferably, at least two adjacent layers of the intermediate structure have substantially equal electron energy work functions. … A vertical field effect transistor is formed in a portion of an intermediate structure by removing areas (30, 31) of the second outer and central layers (4, 3) on each side of the portion, removing an area (32) of the second outer layer (4) at one end of the portion, etching the central layer (3) to form a web (22) connecting the first and second outer layers (2, 4), forming insulation (25, 27) on the exposed surfaces of the first and second outer layers (2, 4), forming a Schottky barrier electrode (23, 24) on the web and providing electrical contacts (35) to the first and second outer layers.

    SRAM cell contg. self-retaining switches
    6.
    发明专利
    SRAM cell contg. self-retaining switches 未知

    公开(公告)号：DE4442358A1

    公开(公告)日：1995-06-08

    申请号：DE4442358

    申请日：1994-11-29

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  DAVARI BIJAN ,  SAI-HALASZ GEORGE ANTHONY ,  TAUR YUAN

    IPC: G11C11/412 ,  H01L27/11 ,  H01L21/8244

    Abstract: Memory self-retaining switch formed on a semiconductor substrate comprises: (a) a gate insulating layer on the substrate; (b) shallow trenches formed through the insulating layer and in the substrate acting as insulation for the building block; (c) doped regions in the substrate between the shallow trenches, the doped regions defining source and drain regions; (d) gate stacks on top of regions of the oxide next to the doped regions; (e) a planarised insulator formed between the gate stacks; (f) openings in the planarised insulator for contacts to the doped regions and the gate stacks; (g) conducting material filling the openings to form contacts for the doped regions and the gate stacks; and (h) a patterned layer of a conducting material on top of the planarised insulator to connect selected contacts for wiring of the self-retaining switching. Also claimed is an SRAM-cell of six constructional units formed on a silicon substrate comprising: (i) a deep insulation trench formed in the substrate; (ii) a first self-retaining switch including two transistors (3,4) of p-conducting material which are formed on one side of the trench; (iii) a second self-retaining switch including two transistors (1,2) of n-conducting material formed on the second side of the trench opposite the first side; (iv) connector for cross-wise wiring of the transistors of the first self-retaining switch with the transistors of the second self-retaining switch, the connector comprising a conductor arranged perpendicular to the trench; and (v) two access transistors (5,6) arranged on the second side of the trench for access to the self-retaining switches. Further claimed is a process for formation of contacts on the diffusion regions and gate stacks on a semiconductor substrate comprising: (A) forming a conformal etch-stop layer on the substrate and the gate stacks; (B) forming a passivation layer on the etch-stop layer with a thickness sufficient to cover the gate stacks; (C) planarising the passivation layer to a height corresponding to the etch-stop layer; (D) forming first openings in the passivation layer and the gate stacks, the openings being so positioned that they border the diffusion regions and are of sufficient depth to make electrical contact to the gate stacks but not with the diffusion regions; (E) forming second opening in the passivation layer and the etch-stop layer bordering the gate stacks and being of sufficient depth to make contact with the diffusion regions, but being of insufficient depth on the gate stacks to make electrical contact with the gate stacks; and (F) filling the first openings and the second openings with a conducting material which forms the contacts.

    7.
    发明专利
    未知

    公开(公告)号：DE68915608D1

    公开(公告)日：1994-07-07

    申请号：DE68915608

    申请日：1989-03-08

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  LIEN YEONG-CHANG ,  TANG JEFFREY YUH-FONG

    IPC: G11C11/41 ,  G11C8/12 ,  G11C8/00

    Abstract: A transposable memory architecture for providing equally fast access to stored data in two or more dimensions. This architecture is provided by orthogonal wiring of access devices, word lines and bit lines with independent random accessing capability for data in each direction. The transposable memory architecture (TMA) cell directly implements the TMA architecture using only one access device per dimension of access. This invention also describes multiple transposable memory architecture (MTMA) device for additional data path flexibility. The read and write operations described provide access and cycle times approximately equivalent to those for a convention one-dimension RAM.

    8.
    发明专利
    未知

    公开(公告)号：DE3485193D1

    公开(公告)日：1991-11-28

    申请号：DE3485193

    申请日：1984-06-08

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  HSIEH HUNG-HUI

    IPC: G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G11C19/38 ,  G06F5/00

    Abstract: A digital shifter/rotator (1000) for shifting an input word by an amount depending on a shift control word (4000) is described. The shifter/rotator comprises an array of FET pass transistors arranged in a sequential number of stages (1200, 1400, 1600, 1700, 1800). The amount to be shifted in each stage is controlled by a corresponding shift control bit on lines 4200 of the shift control word buffered by drivers 4500, whereby the output word of the rotator is the input word shifted by an amount equal to a sum of the number of shifts effected in each of the stages as determined by the shift control word. The rotator features selectable amount of shift in one machine cycle, high performance and reduced device count. Further improved performance is obtained by utilizing decoupling devices for isolating the input points of the stages, except when providing rotation, from the long rotation cross buses and its associated large parasiticcapac- itances.

    9.
    发明专利
    未知

    公开(公告)号：DE68917953T2

    公开(公告)日：1995-03-30

    申请号：DE68917953

    申请日：1989-02-02

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  CHAPPELL TERRY IVAN ,  SCHUSTER STANLEY EVERETT

    IPC: G11C11/413 ,  G11C8/10 ,  G11C11/408 ,  G11C8/00

    Abstract: A high performance decoder/driver circuit for a semiconductor memory having A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A phi PC line is included for receiving a phi PC precharge clock signal thereon and a phi R line is provided for receiving a phi R reset clock signal thereon. The decoder/driver circuit includes an OR decoder means having a plurality of transistor switching devices (1-7) connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on an OR decoder output node (16) depending on the address bits state. The decoder/driver circuit further includes a selection means (8-11) having a plurality of transistor devices including p-channel devices, having diffusion contacts connected to the output node (17, 18) of the decoder and to AN and AN lines to produce a first selection signal when the OR decoder output node is low and the AN line is high and a second selection signal when the OR decoder output node is low and the AN line is high. A driver circuit is connected to the selection means and is responsive to the first selection signal to provide an output signal on a first memory word line (WLi) and is further responsive to the second selection signal to provide an output signal on a second memory word line (WLi+1).

    10.
    发明专利
    未知

    公开(公告)号：DE3685341D1

    公开(公告)日：1992-06-25

    申请号：DE3685341

    申请日：1986-01-09

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  RAJEEVAKUMAR THEKKEMADATHIL VE ,  SCHUSTER STANLEY EVERETT ,  TERMAN LEWIS MADISON

    IPC: H03K19/096 ,  G11C8/10 ,  G11C11/34 ,  G11C11/407 ,  G11C11/413 ,  G11C8/00

    Abstract: A decoder/driver circuit for a semiconductor memory having A1 to AN (true) and At to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A Ø PC line is included for receiving a Ø PC precharge clock signal thereon and a Ø R line is provided for receiving a 0 R reset clock signal thereon.The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices 41...44 connected to A1 to AN-1 orA1 toAN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node 1 4 depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices 24, 28 connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the AN line is high. A driver circuit is connected to the selection means and is responsive to the output signal of the NOR decoder circuit and the first selection signal to provide an output signal on a first memory word line WLi and is further responsive to the output signal of the NOR decoder circuit and the second selection signal to provide an output sigraal on a second memory word line WLi + 1 .

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