公开(公告)号：US3728592A

公开(公告)日：1973-04-17

申请号：US3728592D

申请日：1971-09-14

Applicant: IBM

Inventor： JOSHI M ,  TSU HSING YEH ,  MASTERS B ,  VIVA O

IPC: H01L21/00 ,  H01L21/8222 ,  H01L7/44 ,  H01L9/12 ,  H01L19/00

CPC classification number: H01L21/8222 ,  H01L21/00 ,  Y10S438/904

Abstract: A method of fabricating high-speed planar transistor structures by reducing carrier lifetime through doping with carrier lifetime killers. Gold is diffused through the front surface of the silicon structure during transistor fabrication. The gold is introduced from the vapor phase in a controlled manner so that its solid solubility in silicon is not exceeded. A simultaneous gold and base diffusion is preferred. Such a simultaneous diffusion produces a novel planar transistor structure having a gold distribution curve with an unexpected increased concentration peak in the region proximate to the basecollector junction.

Abstract translation: 一种制造高速平面晶体管结构的方法，通过掺杂载流子寿命抑制剂减少载流子寿命。 在晶体管制造期间，金通过硅结构的前表面扩散。 以受控的方式从气相中引入金，使得其在硅中的固溶度不被超过。 同时的金和碱扩散是优选的。

公开(公告)号：BR7803995A

公开(公告)日：1979-04-03

申请号：BR7803995

申请日：1978-06-23

Applicant: IBM

Inventor： PRICER W ,  JOSHI M

IPC: G11C11/419 ,  G11C11/403 ,  G11C11/405 ,  G11C11/42 ,  G11C11/24 ,  G11C11/34 ,  H01L27/02

Abstract: A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.