公开(公告)号：US3798606A

公开(公告)日：1974-03-19

申请号：US3798606D

申请日：1971-12-17

Applicant: IBM

Inventor： PRICER W ,  HENLE R ,  MALEY G

IPC: G06F12/16 ,  G06F1/00 ,  G06F7/00 ,  G06F11/10 ,  G06F11/18 ,  G06F15/78 ,  H03H9/02 ,  G06F11/00 ,  G06F13/00

CPC classification number: G06F11/184 ,  G06F1/00 ,  G06F7/00 ,  G06F11/10

Abstract: A monolithic circuit bit partitioned computer system for processing M bits of data comprising a substrate for providing electrical interconnection paths to a plurality of M monolithic circuit modules. Each of the M modules includes distinct decoder means, memory means, elemental quasi-arithmetic means and control circuitry, and each of the M modules are uniquely associated with the distinct ones of the M bits of data for collectively and universally processing the M bits of data.

Abstract translation: 一种用于处理M位数据的单片电路位分割计算机系统，包括用于提供到多个M个单片电路模块的电互连路径的衬底。 每个M个模块包括不同的解码器装置，存储装置，元素准运算装置和控制电路，并且M个模块中的每一个与M个数据位中的不同的一个数据唯一地相关联，用于共同和普遍地处理M位 数据。

公开(公告)号：US3740723A

公开(公告)日：1973-06-19

申请号：US3740723D

申请日：1970-12-28

Applicant: IBM

Inventor： BEAUSOLEIL W ,  HO I ,  PRICER W

IPC: G06F12/08 ,  G11C11/415 ,  G11C19/00 ,  G11C9/00 ,  G11C11/34

CPC classification number: G11C19/00 ,  G06F12/0864 ,  G11C11/415

Abstract: A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.

公开(公告)号：US3739356A

公开(公告)日：1973-06-12

申请号：US3739356D

申请日：1971-06-21

Applicant: IBM

Inventor： PRICER W

IPC: G11C11/36 ,  H01L21/00 ,  H01L29/00 ,  G11C5/02

CPC classification number: H01L21/00 ,  G11C11/36 ,  H01L29/00 ,  Y10S257/926

Abstract: A bistable information storage unit which has a semiconductor device having two P-N heterojunctions arranged in opposing series relation. The heterojunctions each exhibit stable high and low impedance states due to a high density of material imperfections, including deep energy traps. In normal operation, the order of the impedance states of the heterojunctions of the device can be sensed and changed. The state or order of the junctions can be used to designate binary information.

Abstract translation: 双稳态信息存储单元，其具有以相对的串联关系布置的两个P-N异质结的半导体器件。 由于高密度的材料缺陷，包括深能量陷阱，异质结各自表现出稳定的高和低阻抗状态。 在正常操作中，可以检测和改变器件的异质结的阻抗状态的顺序。 交点的状态或顺序可用于指定二进制信息。

公开(公告)号：CA935919A

公开(公告)日：1973-10-23

申请号：CA158250

申请日：1972-12-05

Applicant: IBM

Inventor： MORTON R ,  PRICER W ,  GATES H ,  HENLE R ,  NORTH W ,  CASTRUCCI P ,  MASON J

公开(公告)号：SE348580B

公开(公告)日：1972-09-04

申请号：SE40768

申请日：1968-01-12

Applicant: IBM

Inventor： LINDQUIST A ,  PRICER W ,  SEEBER R

IPC: G11C15/04 ,  G11C15/00

Abstract: 1,188,666. Associative stores; read-only stores. INTERNATIONAL BUSINESS MACHINES CORP. 15 Dec., 1967 [13 Jan., 1967], No. 57023/67. Headings G4A and G4C. Each word in a matrix associative memory has a unique address field. Each word in the transistorized memory has an erasable data field and a read-only address field, the address fields specifying the word locations and thus being all different. An input register has a data field and an address field, and by masking off one of them an associative search may be done on the data fields or the address fields, the matching word or words being read out to an output register. The output register also receives an indication of the number of matches (0, 1 or a plurality) provided by logic fed by the output of the address fields since in the case of more than one match at least one address bit position will be indicated as being both 1 and 0 (on separate lines) and in the case of no match any particular bit will not be indicated as being either.

公开(公告)号：BR7803995A

公开(公告)日：1979-04-03

申请号：BR7803995

申请日：1978-06-23

Applicant: IBM

Inventor： PRICER W ,  JOSHI M

IPC: G11C11/419 ,  G11C11/403 ,  G11C11/405 ,  G11C11/42 ,  G11C11/24 ,  G11C11/34 ,  H01L27/02

Abstract: A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.

公开(公告)号：BR7701807A

公开(公告)日：1978-01-24

申请号：BR7701807

申请日：1977-03-22

Applicant: IBM

Inventor： PRICER W

IPC: G11C11/56 ,  G11C5/02 ,  G11C11/24 ,  G11C11/34 ,  G11C11/35 ,  H01L27/10 ,  H01L27/108

Abstract: A semiconductor memory produced in a unipolar technology includes a cell which has an inversion capacitor with one terminal connected to a bit/sense line, the other terminal is coupled to a source of charges by a pulse from a word line. To provide a word organized array of these cells, each word includes a source of charges produced at the surface of a semiconductor substrate and plurality of inversion capacitors are formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the capacitors by applying voltages of two different magnitudes, representing 1 and 0 bits of information, to one terminal of the capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the charge source with each of the capacitors. The capacitors having the larger voltage store the greater amount of charge. This charge can then be detected by measuring the voltage across the storage capacitors when a work pulse again connects the charge source with each of the capacitors.

公开(公告)号：SE366864B

公开(公告)日：1974-05-06

申请号：SE1253370

申请日：1970-09-15

Applicant: IBM

Inventor： CASTRUCCI P ,  GATES H ,  HENLE R ,  PRICER W ,  MORTON R ,  MASON J ,  NORTH W

IPC: F22B21/06 ,  G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  H01L23/525 ,  H01L27/00 ,  H01L27/102 ,  G11C17/00

Abstract: A read only memory having the capability of being written into once after manufacture. The cells of the memory are capable of being fused or permanently altered by directing a fusing current to the selected cells. The cell is a monolithic semiconductor device comprising a diode to be biased in a forward direction and a diode to be biased in the reverse direction structured so as to form back-to-back diodes. The reverse diode has a lower reverse breakdown voltage than the forward diode, and a metal connection, unconnected to any remaining circuit elements contacts the semiconductor device between diode junctions. The fusing current causes a metal-semiconductor alloy to form and short out the reverse diode.

公开(公告)号：CA939076A

公开(公告)日：1973-12-25

申请号：CA100736

申请日：1970-12-16

Applicant: IBM

Inventor： ORDEMANN F JR ,  BEAUSOLEIL W ,  PRICER W ,  VOGL N JR

IPC: G06F3/08 ,  G11C7/00 ,  G11C11/00

公开(公告)号：CA936597A

公开(公告)日：1973-11-06

申请号：CA69790

申请日：1969-12-15

Applicant: IBM

Inventor： PRICER W

IPC: G11C5/06 ,  G11C5/14 ,  G11C11/411 ,  G11C11/414 ,  G11C11/415 ,  H01L27/02 ,  H01L27/10

Abstract: 1,234,709. Bi-stable stores. INTERNATIONAL BUSINESS MACHINES CORP. 15 Dec., 1969 [15 Jan., 1969], No. 60960/69. Heading G4C. A plurality of bi-stable cells 10, 11 is fed from a single power source which is switchable to act as a constant current source supplying a relatively low current when the cells are passively storing, and as a constant voltage source supplying a relatively high current when the state of a cell is to be changed. The constant current effect is achieved with a resistor 18 which is large in comparison with the impedance of the cells, and the constant voltage effect is achieved by shorting out R18 by a transistor 21. A number of separate sets of bi-stables (24, 25, 26, Fig. 2, not shown) each with its own supply, may be arranged on a single or separate chips.