公开(公告)号：AU2021382976A9

公开(公告)日：2025-01-09

申请号：AU2021382976

申请日：2021-11-02

Applicant: IBM

Inventor： KANG MINGU ,  WOO SEONGHOON ,  LEE EUN KYUNG

IPC: G06F7/483

Abstract: A system comprises a floating-point computation unit configured to perform a dot-product operation in accordance with a first floating-point value and a second floating-point value, and detection logic operatively coupled to the floating-point computation unit. The detection logic is configured to compute a difference between fixed-point summations of exponent parts of the first floating-point value and the second floating-point value and, based on the computed difference, detect the presence of a condition prior to completion of the dot-product operation by the floating-point computation unit. In response to detection of the presence of the condition, the detection logic is further configured to cause the floating-point computation unit to avoid performing a subset of computations otherwise performed as part of the dot-product operation. Such techniques serve as a predictor that the avoided subset of computations would have resulted in a dot product of the two floating-point values being below a threshold value.

公开(公告)号：AU2021254857A1

公开(公告)日：2022-08-04

申请号：AU2021254857

申请日：2021-03-01

Applicant: IBM

Inventor： KIM SEYOUNG ,  KANG MINGU ,  KIM KYU-HYOUN ,  WOO SEONGHOON

IPC: G11C27/02 ,  H03M1/66

Abstract: A differential mixed-signal logic processor is provided.The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B.Each of plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors.A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.