公开(公告)号：DE112012000850T8

公开(公告)日：2014-05-28

申请号：DE112012000850

申请日：2012-01-30

Applicant: IBM

Inventor： PONOTH SHOM ,  HORAK DAVID V ,  KOBURGER III CHARLES W ,  YANG CHIH-CHAO

IPC: H01L21/336 ,  H01L21/31 ,  H01L29/78

公开(公告)号：DE69004932T2

公开(公告)日：1994-05-19

申请号：DE69004932

申请日：1990-06-01

Applicant: IBM

Inventor： KERBAUGH MICHAEL L ,  KOBURGER III CHARLES W ,  MACHESNEY BRIAN J

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

Abstract: A method of forming a planarized dielectric filled wide shallow trench (14) in a semiconductor substrate (10) is provided. A layer of etch stop (12) such as Si3N4 is deposited onto the semiconductor substrate (10), and wide trenches (14) are formed through the Si3N4 into the substrate (10) by conventional RIE. The surface of the substrate (10) including the trenches (14) have formed thereon a SiO2 coating (18), conforming to the surface of the substrate (10). A layer of etch resistant material (20) such as polysilicon is deposited onto the SiO2 material (18). The polysilicon (20) outside the width of the trenches (14) is then removed by chemical-mechanical polishing to expose the SiO2 there below, while leaving the SiO2 above the trenches (14) covered with polysilicon (20). The exposed SiO2 is then RIE etched down to the Si , leaving a plug of SiO2 capped with the etch resistant polysilicon (20) over each trench (14). These plugs are then removed by mechanical polishing down to the Si3N4, to provide a planarized upper surface of SiO2 and Si on the top of the substrate (10). The invention also is useful in forming planarized surfaces on substrates (10) having trenches (14) filled with conductive material.

公开(公告)号：DE112012000850T5

公开(公告)日：2013-12-12

申请号：DE112012000850

申请日：2012-01-30

Applicant: IBM

Inventor： PONOTH SHOM ,  HORAK DAVID V ,  KOBURGER III CHARLES W ,  YANG CHIH-CHAO

IPC: H01L21/336 ,  H01L21/31 ,  H01L29/78

Abstract: Ausführungsformen der vorliegenden Erfindung stellen ein Verfahren zum Ausbilden einer Halbleiterstruktur bereit. Das Verfahren beinhaltet ein Bilden einer Öffnung (311) im Innern einer dielektrischen Schicht (201), wobei die dielektrische Schicht auf einer Oberseite eines Substrats (101) ausgebildet wird und die Öffnung einen Kanalbereich (102) eines Transistors (110) in dem Substrat freilegt; ein Abscheiden einer Austrittsarbeitsschicht (401), die die Öffnung auskleidet und den Kanalbereich bedeckt; ein Ausbilden eines Gate-Leiters (610), der einen ersten Abschnitt (411) der Austrittsarbeitsschicht bedeckt, wobei sich der erste Abschnitt der Austrittsarbeitsschicht auf einer Oberseite des Kanalbereichs befindet; und ein Entfernen eines zweiten Abschnitts der Austrittsarbeitsschicht, wobei der zweite Abschnitt der Austrittsarbeitsschicht den ersten Abschnitt der Austrittsarbeitsschicht umgibt; wobei das Entfernen des zweiten Abschnitts der Austrittsarbeitsschicht den ersten Abschnitt der Austrittsarbeitsschicht gegenüber der verbleibenden Austrittsarbeitsschicht (412) isoliert.

公开(公告)号：DE69004932D1

公开(公告)日：1994-01-13

申请号：DE69004932

申请日：1990-06-01

Applicant: IBM

Inventor： KERBAUGH MICHAEL L ,  KOBURGER III CHARLES W ,  MACHESNEY BRIAN J

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

Abstract: A method of forming a planarized dielectric filled wide shallow trench (14) in a semiconductor substrate (10) is provided. A layer of etch stop (12) such as Si3N4 is deposited onto the semiconductor substrate (10), and wide trenches (14) are formed through the Si3N4 into the substrate (10) by conventional RIE. The surface of the substrate (10) including the trenches (14) have formed thereon a SiO2 coating (18), conforming to the surface of the substrate (10). A layer of etch resistant material (20) such as polysilicon is deposited onto the SiO2 material (18). The polysilicon (20) outside the width of the trenches (14) is then removed by chemical-mechanical polishing to expose the SiO2 there below, while leaving the SiO2 above the trenches (14) covered with polysilicon (20). The exposed SiO2 is then RIE etched down to the Si , leaving a plug of SiO2 capped with the etch resistant polysilicon (20) over each trench (14). These plugs are then removed by mechanical polishing down to the Si3N4, to provide a planarized upper surface of SiO2 and Si on the top of the substrate (10). The invention also is useful in forming planarized surfaces on substrates (10) having trenches (14) filled with conductive material.