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公开(公告)号：GB2103850B
公开(公告)日：1985-03-20
申请号：GB8222691
申请日：1982-08-06
Applicant: IBM
Inventor： BREWER JAMES A , EGGEBRECHT LEWIS C , MCHUGH PATRICIA P , KUMMER DAVID A
IPC: G06F12/02 , G11C11/406 , G11C7/00 , G06F13/00
Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a «D-type» latch (24) whose output, is turn, sets the highest priority DMA channel (0) request line (DREQO), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACKO) indicating the cycle is completed.
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公开(公告)号：CA1172386A
公开(公告)日：1984-08-07
申请号：CA403583
申请日：1982-05-21
Applicant: IBM
Inventor： EGGEBRECHT LEWIS C , KUMMER DAVID A , SAENZ JESUS A
Abstract: SYNCHRONIZATION OF CRT CONTROLLER CHIPS Two controller units controlling a single input/ output device such as a cathode ray tube (CRT) are synchronized by a command signal. Upon appearance of the command signal, the slave controller unit, which may have been running unsynchronized with the master controller, is stopped at the time for vertical retrace and remains stopped until vertical retrace time for the master controller. At this point, the slave controller is restarted in synchronism with the master controller and remains synchronized so long as both master and slave receive the same clock and the same screen refresh parameters.
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公开(公告)号：CA1220293A
公开(公告)日：1987-04-07
申请号：CA458370
申请日：1984-07-06
Applicant: IBM
Inventor： KUMMER DAVID A , SAENZ JESUS A , TRYNOSKY STEPHEN W
Abstract: RASTER SCAN DIGITAL DISPLAY SYSTEM In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.
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公开(公告)号：CA1213676A
公开(公告)日：1986-11-04
申请号：CA458368
申请日：1984-07-06
Applicant: IBM
Inventor： KUMMER DAVID A
Abstract: MEMORY ACCESS SYSTEM FOR A COMPUTER SYSTEM ADAPTED TO ACCEPT A MEMORY EXPANSION MODULE A microcomputer includes a main memory system which is accessed, substantially independantly, by the CPU and a subsystem, for example a video display subsystem. The memory system comprises a base memory and an optional add on expansion memory. When only the base memory is installed, consecutive locations have consecutively numbered addresses, and both the CPU and subsystem access individual locations. When both memories are installed, one has even numbered addresses and the other odd numbered addresses. With both memories installed, the CPU still accesses individual locations, but the subsystem addresses even addresses to obtain, for each access, data from the even address and the next higher odd address, thereby accessing a location in both memories. Thus the memory bandwidth for the subsystem is effectively doubled when the expansion memory is installed.
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公开(公告)号：CA1209276A
公开(公告)日：1986-08-05
申请号：CA458356
申请日：1984-07-06
Applicant: IBM
Inventor： KUMMER DAVID A , WEBB GARY E
Abstract: MICROCOMPUTER SYSTEM EMPLOYING PROGRAM CARTRIDGES A microcomputer system employs internal read-only memory devices and external read-only memory devices in pluggable cartridges. Each cartridge includes jumper links in leads from the external memories through the cartridge socket to a memory select unit and jumper links in leads leading from earth through the cartridge socket to enable inputs of the internal memories. By linking selected ones of the jumper links in the cartridge, the external memory can be used as an add-on memory or as a base memory replacing the internal memory.
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Patent Agency Ranking
公开(公告)号：CA1184315A
公开(公告)日：1985-03-19
申请号：CA434110
申请日：1983-08-08
Applicant: IBM
Inventor： EGGEBRECHT LEWIS C , KUMMER DAVID A
IPC: G11C9/04
Abstract: : Extended Addressing Apparatus and Method For Direct Storage Access Devices A computing system storage addressing apparatus which extends the addressing capability of an address bus to enable direct storage (memory) storage access (DMA) channels to operate simultaneously in the same or different storage page. The computing system includes a processor, a plurality of storage devices, a data bus and an address bus interconnecting the processor and the storage devices, a DMA device controlling connection of a plurality of DMA channels to the address bus and data bus, a plurality of address register means for storing page address signals loaded from the processor, and gating means for gating to the address bus page address signals from an address register means corresponding to a currently active DMA channel.
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公开(公告)号：CA1227585A
公开(公告)日：1987-09-29
申请号：CA457027
申请日：1984-06-20
Applicant: IBM
Inventor： KUMMER DAVID A , SAENZ JESUS A , TRYNOSKY STEPHEN W
IPC: G09G5/00 , G06F3/00 , G06F3/14 , G06F7/02 , G06T7/00 , G09G1/16 , G09G5/02 , G09G5/393 , G09G5/395 , G09G1/00
Abstract: RASTER SCAN DIGITAL DISPLAY SYSTEM WITH DIGITAL COMPARATOR MEANS In a bit mapped raster scan digital display system, a number of maps each contain a single component of the display data and are read together to provide sets of bytes, each set representing eight pel defining groups. A compare system is provided for determining when a pel group in a set of bytes compares with a reference pel defining group. For the, or each, pair of maps, the compare system compares all bits of the two bytes of data with the associated bit of the reference group to provide outputs when a corresponding bit in each of the bytes compares with the two reference bits. When more than two maps are employed the compare outputs related to all of the pairs of maps are combined to provide an output signal when a pel group in a byte from the maps compares with the reference bits. In a modification of the system the comparison can be made between one or more of the maps and the corresponding bit or bits of the compare data.
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公开(公告)号：CA1200921A
公开(公告)日：1986-02-18
申请号：CA461008
申请日：1984-08-14
Applicant: IBM
Inventor： BREWER JAMES A , KUMMER DAVID A , LANGGOOD JOHN K
IPC: H05K1/02
Abstract: There is described a six-layer printed circuit card in which the first, third and sixth layers are signal carrying layers for interconnecting various components forming a personal computer. The second and fifth layers are both ground plane layers and the addition of a second ground plane layer to a printed circuit card reduces the electromagnetic interference emitted from the closely packed components and lines. The final layer of the card is a voltage plane. The components on the printed circuit board include eight input/output (I/O) connectors to which eight other cards controlling various I/O devices can be connected. Seven of the eight I/O connectors are interconnected to a conventional I/O bus. The eight connector is interconnected to some lines of the I/O bus and to some lines of the internal bus throughout the card.
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公开(公告)号：CA1224291A
公开(公告)日：1987-07-14
申请号：CA457026
申请日：1984-06-20
Applicant: IBM
Inventor： KUMMER DAVID A , RACKLEY DARWIN P , SAENZ JESUS A
Abstract: RASTER SCAN DISPLAY SYSTEM A raster scan display system includes a plurality of storage maps. These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide color signals from which color video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.
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公开(公告)号：CA1216955A
公开(公告)日：1987-01-20
申请号：CA458371
申请日：1984-07-06
Applicant: IBM
Inventor： KUMMER DAVID A
Abstract: MEMORY PAGING SYSTEM IN A MICROCOMPUTER In a microcomputer system having a main memory accessed by both the CPU and the CRT controller, a page register system receives page bits defining both CPU and CRT pages from the CPU. The CPU page bits are combined with lower order address bits from the CPU for CPU access cycles, and the CRT page bits are combined with lower order address bits from CRT controller for CRT access cycles. Both the CPU and CRT controller can access any of the pages in the memory. For compatibility with higher level systems, the CPU may provide addresses in a range outside the range of addresses for the memory. When a decoder detects such addresses, it directs CPU address bits, corresponding in order to the CPU page bits, to address the memory instead of the CPU page bits.
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