公开(公告)号：PL319041A1

公开(公告)日：1997-07-21

申请号：PL31904195

申请日：1995-08-31

Applicant: IBM

Inventor： CRUMP DWAYNE THOMAS ,  PANCOAST STEVEN TAYLOR ,  LANDRY JOHN MATTHEW ,  BENSON PAUL HARRISON IV

IPC: G06F1/00 ,  G06F1/30 ,  G06F9/48

Abstract: A computer system having a CPU, a non-volatile storage device, a power management processor having a volatile power management configuration, and a power supply in circuit communication. The power management processor controls the regulation of power to the CPU by the power supply. Prior to causing the power supply to cease providing regulated power to the CPU, the power management processor interrupts the CPU via a system management interrupt. Responsive to being interrupted via the system management interrupt, the CPU performs tasks associated with the power supply imminently ceasing to provide regulated power to the CPU. Such tasks include writing data to non-volatile memory and refreshing an alarm value in the power management processor. The CPU can extend the period of time before the power management processor causes the power supply to cease providing regulated power to the CPU while the CPU performs the necessary tasks.