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    Desktop computer system having multi-level power management
    1.
    发明专利
    Desktop computer system having multi-level power management 未知

    公开(公告)号：AU6591194A

    公开(公告)日：1995-01-05

    申请号：AU6591194

    申请日：1994-06-24

    Applicant: IBM

    Inventor： COMBS JAMES LEE ,  CRUMP DWAYNE THOMAS ,  PANCOAST STEVEN TAYLOR

    IPC: G06F1/32 ,  G06F9/445 ,  G06F9/46 ,  G06F11/14 ,  G06F12/16

    Abstract: A computer system having four states of power management: a normal operating state, a standby state, a suspend state, and an off state. The standby state is characterized by devices, such as a video controller and a hard drive, being placed into a low-power mode transparent to the operating system and the applications executing on the computer system. The suspend state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive. Later, after system power is restored, the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected. The normal operating state and the off state correspond to the typical on and off states of more conventional computer systems. The suspend/resume/standby feature is implemented at a low cost using many standard components.

    Desktop computer system having multi-level power management
    3.
    发明专利
    Desktop computer system having multi-level power management 未知

    公开(公告)号：AU685455B2

    公开(公告)日：1998-01-22

    申请号：AU6591194

    申请日：1994-06-24

    Applicant: IBM

    Inventor： COMBS JAMES LEE ,  CRUMP DWAYNE THOMAS ,  PANCOAST STEVEN TAYLOR

    IPC: G06F1/32 ,  G06F9/445 ,  G06F9/46 ,  G06F11/14 ,  G06F12/16

    Abstract: A computer system having four states of power management: a normal operating state, a standby state, a suspend state, and an off state. The standby state is characterized by devices, such as a video controller and a hard drive, being placed into a low-power mode transparent to the operating system and the applications executing on the computer system. The suspend state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive. Later, after system power is restored, the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected. The normal operating state and the off state correspond to the typical on and off states of more conventional computer systems. The suspend/resume/standby feature is implemented at a low cost using many standard components.

    7.
    发明专利
    未知

    公开(公告)号：DE69634525D1

    公开(公告)日：2005-05-04

    申请号：DE69634525

    申请日：1996-05-13

    Applicant: IBM

    Inventor： CRUMP DWAYNE THOMAS ,  PANCOAST STEVEN TAYLOR

    IPC: G06F9/34 ,  G06F9/38 ,  G06F12/08 ,  G06F12/12 ,  G06F15/78 ,  G06F17/10 ,  G06T1/20 ,  G09G5/00

    Abstract: A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors.

    9.
    发明专利
    未知

    公开(公告)号：DE69601599T2

    公开(公告)日：1999-10-14

    申请号：DE69601599

    申请日：1996-05-13

    Applicant: IBM

    Inventor： CRUMP DWAYNE THOMAS ,  PANCOAST STEVEN TAYLOR

    IPC: G06T1/20 ,  G06F9/312 ,  G06F9/318 ,  G06F9/32 ,  G06F9/355 ,  G06F12/08 ,  G06F15/80 ,  G06T11/00 ,  G09G5/36 ,  G09G5/39 ,  G09G1/16 ,  G09G5/00

    Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor has, on a single VLSI device, a plurality of processors which cooperate for generating video signal streams and which employ distinctive addressing modes for memory elements of the device. Each of the plurality of processors has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors, and further has registers for controlling access, and the modes of access, to data held in memory.

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