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公开(公告)号：AU685455B2
公开(公告)日：1998-01-22
申请号：AU6591194
申请日：1994-06-24
Applicant: IBM
Inventor： COMBS JAMES LEE , CRUMP DWAYNE THOMAS , PANCOAST STEVEN TAYLOR
Abstract: A computer system having four states of power management: a normal operating state, a standby state, a suspend state, and an off state. The standby state is characterized by devices, such as a video controller and a hard drive, being placed into a low-power mode transparent to the operating system and the applications executing on the computer system. The suspend state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive. Later, after system power is restored, the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected. The normal operating state and the off state correspond to the typical on and off states of more conventional computer systems. The suspend/resume/standby feature is implemented at a low cost using many standard components.
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公开(公告)号：DE69122536D1
公开(公告)日：1996-11-14
申请号：DE69122536
申请日：1991-02-21
Applicant: IBM
Inventor： BERTRAM RANDAL LEE , CRUMP DWAYNE THOMAS , FORD JEFFREY VERNON , WELMAN GLENN EUGENE , WRIGHT JOHN PAUL
Abstract: A computer system with read-only memory and permanent read/write memory provides the user with the capability of loading an alternate operating system at the conclusion of a session without turning the computer off and then on. A customization word with a system request (SR) bit is located in read/write memory and is set by routines located in ROM upon user request. A reinitialization is then forced which resets the SR bit and brings up the machine in the alternate operating system located in external memory on a diskette or fixed disk. A flexible initialization system is also disclosed providing customized initialization in a variety of operating systems and applications. The preferred customized initialization is maintained for future system start-ups due to the resetting of the SR bit.
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公开(公告)号：SG70605A1
公开(公告)日：2000-02-22
申请号：SG1997002867
申请日：1997-08-08
Applicant: IBM
Inventor： CRUMP DWAYNE THOMAS , HEANEY JAMES ALFRED , NEVITT CHRIS ALAN
Abstract: Disclosed is a personal computer system that includes a media console coupled to a system unit with a multi-conductor cable. The media console includes a direct access storage device having an opening for receiving a removable storage medium. The system unit is separate from the console and includes a microprocessor coupled to a local bus and an expansion bus, a non-volatile storage device coupled to the local bus and a power supply for supplying power to the system. The cable has one end coupled to the console and another end coupled to the system unit for electrically connecting devices in the console to devices in the system unit. The system unit has a first interface coupled to the expansion bus and the cable, and the console has a second interface coupled to the cable and the direct access storage device in the console. The first interface is operative to (1) determine when a bus cycle initiated by a device in the system unit is directed to the direct access storage device in the console and (2) transfer data from the expansion bus to the direct access storage device via the cable and the second interface when a bus cycle is directed to the direct access storage device.
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公开(公告)号：CZ9901012A3
公开(公告)日：1999-07-14
申请号：CZ101299
申请日：1997-08-22
Applicant: IBM
Inventor： CRUMP DWAYNE THOMAS , CARIDIS JOHN PETER , PANCOAST STEVE , RESNICK RUSSELL ALAN , SCWARTZ ROBERT CHRISTIAN
CPC classification number: G06K13/0825 , G06F1/181
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公开(公告)号：CA2191631A1
公开(公告)日：1997-08-14
申请号：CA2191631
申请日：1996-11-29
Applicant: IBM
Inventor： CRUMP DWAYNE THOMAS , HURD JONATHAN JAMES , PANCOAST STEPHEN TAYLOR , WORTHINGTON THOMAS K
Abstract: Disclosed is a method and apparatus for processing two analog composite vide o signals to be displayed to a human observer. The system includes at least a first an d a second video source for generating first and second analog composite video signals respec tively, and a selector coupled to the first and second video sources. The selector is operative to supply either the first or second analog composite video signal to one input of a video processor an d independently and simultaneously supply either the first or second analog composite video signal to a second input of the video processor. The video processor is operative under contro l of a CPU to generate an output analog composite video signal comprised of a portion of t he analog composite video signal supplied to the video processor's first input and a portion of the analog composite video signal supplied to the video processor's second input.
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Patent Agency Ranking
公开(公告)号：AU6591194A
公开(公告)日：1995-01-05
申请号：AU6591194
申请日：1994-06-24
Applicant: IBM
Inventor： COMBS JAMES LEE , CRUMP DWAYNE THOMAS , PANCOAST STEVEN TAYLOR
Abstract: A computer system having four states of power management: a normal operating state, a standby state, a suspend state, and an off state. The standby state is characterized by devices, such as a video controller and a hard drive, being placed into a low-power mode transparent to the operating system and the applications executing on the computer system. The suspend state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive. Later, after system power is restored, the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected. The normal operating state and the off state correspond to the typical on and off states of more conventional computer systems. The suspend/resume/standby feature is implemented at a low cost using many standard components.
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公开(公告)号：DE69634525D1
公开(公告)日：2005-05-04
申请号：DE69634525
申请日：1996-05-13
Applicant: IBM
Inventor： CRUMP DWAYNE THOMAS , PANCOAST STEVEN TAYLOR
Abstract: A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors.
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公开(公告)号：AU3020600A
公开(公告)日：2000-07-06
申请号：AU3020600
申请日：2000-04-28
Applicant: IBM
Inventor： COMBS JAMES LEE , CRUMP DWAYNE THOMAS , PANCOAST STEVEN TAYLOR
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公开(公告)号：DE69601599T2
公开(公告)日：1999-10-14
申请号：DE69601599
申请日：1996-05-13
Applicant: IBM
Inventor： CRUMP DWAYNE THOMAS , PANCOAST STEVEN TAYLOR
IPC: G06T1/20 , G06F9/312 , G06F9/318 , G06F9/32 , G06F9/355 , G06F12/08 , G06F15/80 , G06T11/00 , G09G5/36 , G09G5/39 , G09G1/16 , G09G5/00
Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor has, on a single VLSI device, a plurality of processors which cooperate for generating video signal streams and which employ distinctive addressing modes for memory elements of the device. Each of the plurality of processors has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors, and further has registers for controlling access, and the modes of access, to data held in memory.
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公开(公告)号：DE69601750T2
公开(公告)日：1999-10-07
申请号：DE69601750
申请日：1996-05-13
Applicant: IBM
Inventor： CRUMP DWAYNE THOMAS , PANCOAST STEVE TAYLOR
Abstract: The VLSI circuit has processors which cooperate to generate video signal streams and two interrupt registers for controlling the operations of instruction data stream execution and interruption.
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