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1.发明专利
公开(公告)号：PL319043A1
公开(公告)日：1997-07-21
申请号：PL31904395
申请日：1995-08-31
Applicant: IBM
Inventor： CRUMP DWAYNE THOMAS , PANCOAST STEVEN TAYLOR , NORRIS DUANE EDWARD , BENSON PAUL HARRISON IV
Abstract: A computer system having four states of power management: a normal operating state, a standby state, a suspend state, and an off state. A control unit controls transitions between the various states. The standby state is characterized by devices, such as a video controller and a hard drive, being placed into a low-power mode transparent to the operating system and the applications executing on the computer system. The suspend state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive. Later, after system power is restored, the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected. The normal operating state and the off state correspond to the typical on and off states of more conventional computer systems. A single switch causes transitions between the various states. A visual feedback device, such as an LED is used to indicate the state of the computer system. While no power management driver is active, the control unit delays state transitions until a suitable power management driver is active.
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2.发明专利
公开(公告)号：PL319041A1
公开(公告)日：1997-07-21
申请号：PL31904195
申请日：1995-08-31
Applicant: IBM
Inventor： CRUMP DWAYNE THOMAS , PANCOAST STEVEN TAYLOR , LANDRY JOHN MATTHEW , BENSON PAUL HARRISON IV
Abstract: A computer system having a CPU, a non-volatile storage device, a power management processor having a volatile power management configuration, and a power supply in circuit communication. The power management processor controls the regulation of power to the CPU by the power supply. Prior to causing the power supply to cease providing regulated power to the CPU, the power management processor interrupts the CPU via a system management interrupt. Responsive to being interrupted via the system management interrupt, the CPU performs tasks associated with the power supply imminently ceasing to provide regulated power to the CPU. Such tasks include writing data to non-volatile memory and refreshing an alarm value in the power management processor. The CPU can extend the period of time before the power management processor causes the power supply to cease providing regulated power to the CPU while the CPU performs the necessary tasks.
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