公开(公告)号：CA1248641A

公开(公告)日：1989-01-10

申请号：CA514222

申请日：1986-07-21

Applicant: IBM

Inventor： CHOW MELANIE M ,  CRONIN JOHN E ,  GUTHRIE WILLIAM L ,  KAANTA CARTER W ,  LUTHER BARBARA J ,  PATRICK WILLIAM J ,  PERRY KATHLEEN A ,  STANDLEY CHARLES L

IPC: H01L21/3205 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H05K3/04 ,  H05K3/10 ,  H05K3/46 ,  H01L21/72

Abstract: Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time. Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material. The channels and via holes are overfilled with metallization. The excess metallization is removed by etching or by chem-mech (chemical-mechanical) polishing.

公开(公告)号：SG72864A1

公开(公告)日：2000-05-23

申请号：SG1998003780

申请日：1998-09-21

Applicant: IBM

Inventor： CRONIN JOHN E ,  LUTHER BARBARA J

IPC: H05K3/46 ,  H01L21/306 ,  H01L21/768 ,  H01L23/12 ,  H01L23/522 ,  H01L23/538

Abstract: A structure and method for connecting two levels of interconnect vertically spaced from each other by another level of interconnect by forming a first interconnect region to which contact is to be made, a first insulating layer over the interconnect region, and an etch-stop layer over the first insulating layer, and etching the etch stop layer to form an opening at a position over the first interconnect region. A second interconnect region is formed in contact with the first insulating layer and above the first interconnect region, a second insulating layer is formed over the first insulation layer and the etch stop layer, and an opening is formed in the second insulating layer overlapping the opening in the etch stop layer. The opening in the second insulating layer is extended through the first insulating layer and the openings in the first and second insulating layers are filled with a conductor to create a connection between the first interconnect region and a region above the second insulating layer.