公开(公告)号：CA1248641A

公开(公告)日：1989-01-10

申请号：CA514222

申请日：1986-07-21

Applicant: IBM

Inventor： CHOW MELANIE M ,  CRONIN JOHN E ,  GUTHRIE WILLIAM L ,  KAANTA CARTER W ,  LUTHER BARBARA J ,  PATRICK WILLIAM J ,  PERRY KATHLEEN A ,  STANDLEY CHARLES L

IPC: H01L21/3205 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H05K3/04 ,  H05K3/10 ,  H05K3/46 ,  H01L21/72

Abstract: Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time. Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material. The channels and via holes are overfilled with metallization. The excess metallization is removed by etching or by chem-mech (chemical-mechanical) polishing.

公开(公告)号：CA2039321A1

公开(公告)日：1991-10-31

申请号：CA2039321

申请日：1991-03-28

Applicant: IBM

Inventor： CRONIN JOHN E ,  KAANTA CARTER W ,  LEE PEI-ING P ,  PREVITI-KELLY ROSEMARY A ,  RYAN JAMES G ,  YOON JUNG H

IPC: G03F5/24 ,  G03F7/038 ,  G03F7/26 ,  G03F7/30 ,  H05K1/05

Abstract: BU9-90-013 PROCESS FOR FORMING MULTI-LEVEL COPLANAR CONDUCTOR/INSULATOR FILM EMPLOYING, PHOTOSENSITIVE POLYIMIDE POLYMER COMPOSITIONS of to Disclosure Disclosed is a process for producing multi-level conductor/insulator films on a processed semiconductor substrate having a conductor pattern. The insulator layers, each comprise a photosensitive polyimide polymer composition, and this allows the desired wiring channels and stud vias to be formed directly in the insulator layers, without the use of separate masking layers and resulting image transfer steps, thus providing a less cumbersome and costly process.

公开(公告)号：CA1306072C

公开(公告)日：1992-08-04

申请号：CA556673

申请日：1988-01-15

Applicant: IBM

Inventor： CRONIN JOHN E ,  KAANTA CARTER W ,  LEACH MICHAEL A ,  LEE PEI-ING P ,  PAN PAI-HUNG

IPC: H01L23/52 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L21/285 ,  H01L29/40 ,  H01L23/48

Abstract: B??-86-011 The present invention provides a conductive structure for use in semiconductor devices. The structure can be used to interconnect the various diffusion regions or electrodes of devices formed on a processed semiconductor substrate to a layer of metal, to interconnect overlying layers of metal or to provide the gate electrode of an FET device formed on the surface of a semiconductor substrate. Various embodiments of the invention are described, but in broad form the active metallurgy of the present invention comprises a thin layer of titanium nitride and a thick layer of a refractory metal, e.g., tungsten or molybdenum, overlying the titanium nitride layer.

公开(公告)号：DE3868178D1

公开(公告)日：1992-03-12

申请号：DE3868178

申请日：1988-07-12

Applicant: IBM

Inventor： CRONIN JOHN E ,  KAANTA CARTER W

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/90

Abstract: A method of forming a conductive structure on a substrate (10) by using both of the via-filling and stud-forming metallization techniques. A stud that is approximately one-half the thickness of the final stud is defined on a conductive layer (12). The stud-forming mask (14) is left in place. Then the sidewalls of the mask are positively tapered, and an insulator layer (16) is deposited on the substrate. The insulator is then etched to expose the stud forming mask, and the mask is removed. The sidewalls of the vias thus defined in the insulator layer are then positively tapered. By positively tapering both the stud mask prior to insulator deposition and the insulator via prior to metal deposition, insulator gap-fill and metal hole-fill problems are eliminated.