公开(公告)号：JPH11261026A

公开(公告)日：1999-09-24

申请号：JP894399

申请日：1999-01-18

Applicant: IBM

Inventor： CANALE ANTHONY J ,  CRONIN JOHN E

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a semiconductor trench capacitor cell having a buried strap. SOLUTION: A substrate has a trench having conductors 28 and 34 separated from a trench wall by dielectric materials 26 and 30. One part of the material 30 is removed from the top surface of the conductor 34 to the low level of the conductor 34 and at least one part of a space formed, in such a way, is filled with a diffusible material 42. The conductor 34, the wall 32 and the material 42 are subjected to annealing to diffuse conductive elements from the wall and the conductors into the material 42, whereby a buried strap 42 is formed.

公开(公告)号：JPH11163246A

公开(公告)日：1999-06-18

申请号：JP26252598

申请日：1998-09-17

Applicant: IBM

Inventor： CRONIN JOHN E ,  BARBARA J LUTHER

IPC: H05K3/46 ,  H01L21/306 ,  H01L21/768 ,  H01L23/12 ,  H01L23/522 ,  H01L23/538

Abstract: PROBLEM TO BE SOLVED: To form through vias without additional mask, by forming a second interconnect area in contact with a first insulating layer on a first interconnect area, forming a second insulating layer on an etching stopping layer, and forming an opening which overlaps with an opening in the etching stopping layer. SOLUTION: A nitride etching stopping layer 42, a polyimide insulating layer 44, a nitride etching stopping layer 46, a polyimide insulating layer 48 and nitride etching stopping layer, are deposited in sequence to form a stack. The etching stopping layer 42 is directly deposited on an etching stopping layer 26 in a partial contact with it. This forms a 'hidden mask area'. A resist layer 52 is developed to expose a part of the top of the nitride etching stopping layer 50 and to mark an opening which forms an M3 via interconnect area 54 and multilayer through via multiple connection area 57. In this way, a multilayer through via can be formed through the use of the hidden mask image without additional mask nor interconnect resistor.

公开(公告)号：JPH10289949A

公开(公告)日：1998-10-27

申请号：JP9198298

申请日：1998-04-03

Applicant: IBM

Inventor： CRONIN JOHN E ,  HARTSWICK THOMAS J ,  STAMPER ANTHONY K

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To facilitate mutual connection between a connecting wire and a mutual connection stud by using a sidewall spacer on the side face of the connecting wire for widening the contact area between the connecting wire and the connection stud. SOLUTION: A semiconductor part 100 has a connection stud 102 connecting the first connecting wire 104 to the second connecting wire 106. The first connecting wire 104 and the second connecting wire 106 and made of a metallic conductor in high conductivity. A substitute conductive path is formed between the first connecting wire 104 and the mutual connection stud 102 by a sidewall spacer 2 added to the first connecting wire 104 before an insulator is bonded. Especially, the side wall 22 comes into contact with a Ti/TiN layer 108 along the outer side thereof. Furthermore, the connection stud 102 is connected to the sidewall spacer 122 which is further connected to the first connecting wire 104. Accordingly, the sidewall spacer 122 is connected to the first connecting wire 104 along the whole sidewall thereof.

公开(公告)号：CA1306072C

公开(公告)日：1992-08-04

申请号：CA556673

申请日：1988-01-15

Applicant: IBM

Inventor： CRONIN JOHN E ,  KAANTA CARTER W ,  LEACH MICHAEL A ,  LEE PEI-ING P ,  PAN PAI-HUNG

IPC: H01L23/52 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L21/285 ,  H01L29/40 ,  H01L23/48

Abstract: B??-86-011 The present invention provides a conductive structure for use in semiconductor devices. The structure can be used to interconnect the various diffusion regions or electrodes of devices formed on a processed semiconductor substrate to a layer of metal, to interconnect overlying layers of metal or to provide the gate electrode of an FET device formed on the surface of a semiconductor substrate. Various embodiments of the invention are described, but in broad form the active metallurgy of the present invention comprises a thin layer of titanium nitride and a thick layer of a refractory metal, e.g., tungsten or molybdenum, overlying the titanium nitride layer.

公开(公告)号：SG63828A1

公开(公告)日：1999-03-30

申请号：SG1998000565

申请日：1998-03-14

Applicant: IBM

Inventor： CRONIN JOHN E ,  HARTSWICK THOMAS J ,  STAMPER ANTHONY K

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/01

Abstract: The preferred embodiment of the present invention provides increased conductivity between interlevel interconnection lines. The preferred embodiment uses sidewall spacers on the sides of the interconnection lines to increase the contact area between interconnection lines and interconnect studs. This increase in area improves connection resistance and allows further device scaling without unacceptable decreases in the conductivity of the connection, and without adding significant expense in the fabrication process.

公开(公告)号：CA1248641A

公开(公告)日：1989-01-10

申请号：CA514222

申请日：1986-07-21

Applicant: IBM

Inventor： CHOW MELANIE M ,  CRONIN JOHN E ,  GUTHRIE WILLIAM L ,  KAANTA CARTER W ,  LUTHER BARBARA J ,  PATRICK WILLIAM J ,  PERRY KATHLEEN A ,  STANDLEY CHARLES L

IPC: H01L21/3205 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H05K3/04 ,  H05K3/10 ,  H05K3/46 ,  H01L21/72

Abstract: Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time. Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material. The channels and via holes are overfilled with metallization. The excess metallization is removed by etching or by chem-mech (chemical-mechanical) polishing.

公开(公告)号：MY117252A

公开(公告)日：2004-06-30

申请号：MYPI9800951

申请日：1998-03-04

Applicant: IBM

Inventor： CRONIN JOHN E ,  HARTSWICK THOMAS J ,  STAMPER ANTHONY K

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/42 ,  H01L23/522 ,  H01L23/532 ,  H01L27/01 ,  H01L29/40

Abstract: THE PREFERRED EMBODIMENT OF THE PRESENT INVENTION PROVIDES INCREASED CONDUCTIVITY BETWEEN INTERLEVEL INTERCONNECTION LINES (104, 304, 521). THE PREFERRED EMBODIMENT USES SIDEWALL SPACERS (120, 122,320,322,520, 522) ON THE SIDES OF THE INTERCONNECTION LINES TO INCREASE THE CONTACT AREA BETWEEN INTERCONNECTION LINES AND INTERCONNECT STUDS (102). THIS INCREASE IN AREA IMPROVES CONNECTION RESISTANCE AND ALLOWS FURTHER DEVICE SCALING WITHOUT UNACCEPTABLE DECREASES IN THE CONDUCTIVITY OF THE CONNECTION, AND WITHOUT ADDING SIGNIFICANT EXPENSE IN THE FABRICATION PROCESS.

公开(公告)号：SG72864A1

公开(公告)日：2000-05-23

申请号：SG1998003780

申请日：1998-09-21

Applicant: IBM

Inventor： CRONIN JOHN E ,  LUTHER BARBARA J

IPC: H05K3/46 ,  H01L21/306 ,  H01L21/768 ,  H01L23/12 ,  H01L23/522 ,  H01L23/538

Abstract: A structure and method for connecting two levels of interconnect vertically spaced from each other by another level of interconnect by forming a first interconnect region to which contact is to be made, a first insulating layer over the interconnect region, and an etch-stop layer over the first insulating layer, and etching the etch stop layer to form an opening at a position over the first interconnect region. A second interconnect region is formed in contact with the first insulating layer and above the first interconnect region, a second insulating layer is formed over the first insulation layer and the etch stop layer, and an opening is formed in the second insulating layer overlapping the opening in the etch stop layer. The opening in the second insulating layer is extended through the first insulating layer and the openings in the first and second insulating layers are filled with a conductor to create a connection between the first interconnect region and a region above the second insulating layer.

公开(公告)号：CA2039321A1

公开(公告)日：1991-10-31

申请号：CA2039321

申请日：1991-03-28

Applicant: IBM

Inventor： CRONIN JOHN E ,  KAANTA CARTER W ,  LEE PEI-ING P ,  PREVITI-KELLY ROSEMARY A ,  RYAN JAMES G ,  YOON JUNG H

IPC: G03F5/24 ,  G03F7/038 ,  G03F7/26 ,  G03F7/30 ,  H05K1/05

Abstract: BU9-90-013 PROCESS FOR FORMING MULTI-LEVEL COPLANAR CONDUCTOR/INSULATOR FILM EMPLOYING, PHOTOSENSITIVE POLYIMIDE POLYMER COMPOSITIONS of to Disclosure Disclosed is a process for producing multi-level conductor/insulator films on a processed semiconductor substrate having a conductor pattern. The insulator layers, each comprise a photosensitive polyimide polymer composition, and this allows the desired wiring channels and stud vias to be formed directly in the insulator layers, without the use of separate masking layers and resulting image transfer steps, thus providing a less cumbersome and costly process.

公开(公告)号：DE3868178D1

公开(公告)日：1992-03-12

申请号：DE3868178

申请日：1988-07-12

Applicant: IBM

Inventor： CRONIN JOHN E ,  KAANTA CARTER W

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/90

Abstract: A method of forming a conductive structure on a substrate (10) by using both of the via-filling and stud-forming metallization techniques. A stud that is approximately one-half the thickness of the final stud is defined on a conductive layer (12). The stud-forming mask (14) is left in place. Then the sidewalls of the mask are positively tapered, and an insulator layer (16) is deposited on the substrate. The insulator is then etched to expose the stud forming mask, and the mask is removed. The sidewalls of the vias thus defined in the insulator layer are then positively tapered. By positively tapering both the stud mask prior to insulator deposition and the insulator via prior to metal deposition, insulator gap-fill and metal hole-fill problems are eliminated.