公开(公告)号：DE2327792A1

公开(公告)日：1974-01-17

申请号：DE2327792

申请日：1973-06-01

Applicant: IBM

Inventor： MALEY GERALD ADRIAN ,  RISEMAN JACOB

IPC: G06F9/50 ,  G06F11/34 ,  G06F9/00

公开(公告)号：DE3465231D1

公开(公告)日：1987-09-10

申请号：DE3465231

申请日：1984-11-14

Applicant: IBM

Inventor： MALEY GERALD ADRIAN ,  WESTCOTT DOUGLAS WAYNE

IPC: H03K3/037 ,  H03K5/135

Abstract: An edge triggered polarity hold, clocked latch circuit is disclosed which requires the use of only a single clock line for operation. The latch circuit comprises three set-reset type latches (1, 2, 3). Each of two latches (1, 2) receives one set and one reset signal. The third latch (3) receives two reset signals and one set signal. A single clock signal is applied jointly to a reset terminal of the third latch (3) and of one of the first two latches (1, 2). A data signal is applied to the set terminal of the third latch (3). The other of the first two latches (1,2) constitutes the output latch (2) and is connected to receive the outputs of the remaining latches. The output latch (2) produces an output equal to an input data signal upon each occurrence of the leading edge of an input clock signal. The output is held (latched) until the occurrence of the next clock signal when the output becomes equal to the then existing input data signal.

公开(公告)号：DE1166820B

公开(公告)日：1964-04-02

申请号：DEJ0018815

申请日：1960-10-05

Applicant: IBM

Inventor： MALEY GERALD ADRIAN

IPC: H03K3/033 ,  H03K19/09

公开(公告)号：DE3380388D1

公开(公告)日：1989-09-14

申请号：DE3380388

申请日：1983-02-28

Applicant: IBM

Inventor： MALEY GERALD ADRIAN ,  WARREN RAYMOND HENRY ,  WESTCOTT DOUGLAS WAYNE

IPC: H03K3/037

Abstract: A hazard-free latch is disclosed comprising three NAND logic gates (1-3), one of the gates (3), in combination with its loading, being relatively fast and another of the gates (2), in combination with its output loading, being relatively slow. Both gates receive an input clock signal. Input data is applied to the third gate (1). The output of the fast gate (3) is connected to another input of the slow gate (2). The outputs of the third (1) and the slow gates (2) are connected to an output terminal and to another input of the fast gate (3).

公开(公告)号：AT28770T

公开(公告)日：1987-08-15

申请号：AT84113733

申请日：1984-11-14

Applicant: IBM

Inventor： MALEY GERALD ADRIAN ,  WESTCOTT DOUGLAS WAYNE

IPC: H03K3/037 ,  H03K5/135

Abstract: An edge triggered polarity hold, clocked latch circuit is disclosed which requires the use of only a single clock line for operation. The latch circuit comprises three set-reset type latches (1, 2, 3). Each of two latches (1, 2) receives one set and one reset signal. The third latch (3) receives two reset signals and one set signal. A single clock signal is applied jointly to a reset terminal of the third latch (3) and of one of the first two latches (1, 2). A data signal is applied to the set terminal of the third latch (3). The other of the first two latches (1,2) constitutes the output latch (2) and is connected to receive the outputs of the remaining latches. The output latch (2) produces an output equal to an input data signal upon each occurrence of the leading edge of an input clock signal. The output is held (latched) until the occurrence of the next clock signal when the output becomes equal to the then existing input data signal.

公开(公告)号：DE3854012D1

公开(公告)日：1995-07-27

申请号：DE3854012

申请日：1988-02-24

Applicant: IBM

Inventor： MALEY GERALD ADRIAN ,  WEITZEL STEPHEN DOUGLAS ,  MOSLEY JOSEPH MICHAEL

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/007

Abstract: A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one of the first and second interconnected signal paths.

公开(公告)号：DE3167582D1

公开(公告)日：1985-01-17

申请号：DE3167582

申请日：1981-06-16

Applicant: IBM

Inventor： MALEY GERALD ADRIAN

IPC: H04L1/00 ,  G05F1/46 ,  H03K5/1252 ,  H03K19/003 ,  H04L25/02 ,  H04L25/08 ,  H03K5/01

Abstract: The generation of internal circuit noise due to the switching of differing numbers of bilevel data lines is suppressed by maintaining the energizing current substantially constant with widely varying amounts of current drawn by varying the current drawn by redundant driver circuits, which also generate parity or check signals, to compensate for the difference in current drawn by the designated data driver circuits. The number of redundant driver circuits is reduced by loading the second and further redundant driver circuits for drawing currewnts related to the current drawn by the first redundant driver circuit by succeeding powers of two. Further suppression in internal circuit noise obtains with gating of all driver circuits at the time switching occurs. Control circuitry comprising conventional full adder circuits arranged for expressing the number of data signal lines in a given level is advantageous for controlling the redundant driver circuits and for generating check bits at the same time.

公开(公告)号：DE2311994A1

公开(公告)日：1973-10-25

申请号：DE2311994

申请日：1973-03-10

Applicant: IBM

Inventor： HO IRVING TZE ,  MALEY GERALD ADRIAN ,  YU HWA NIEN

IPC: G11C17/00 ,  G11C7/20 ,  G11C11/35 ,  G11C11/404 ,  G11C17/12 ,  H01L27/108 ,  G11C11/40

Abstract: A latent image memory is selectively operable as either a read-write memory or a read-only memory. The memory comprises an array of cells each preferably consisting of a single active device. A first set of the cells are each adapted to store either one of two binary digits. A second set of the cells are each responsive to a first condition for storing either one of two binary digits and responsive to a second condition for storing only a single predetermined binary digit. Means are provided for selecting either the first condition to render the array operable as a read-write memory, or the second condition to render the array operable as a read-only memory. Each of the cells of the first set preferably comprises a field-effect transistor connected to a capacitor, and each of the cells of the second set preferably comprises a charge-coupled device.

公开(公告)号：DE1154832B

公开(公告)日：1963-09-26

申请号：DEJ0018816

申请日：1960-10-05

Applicant: IBM

Inventor： MALEY GERALD ADRIAN

IPC: G06F1/04 ,  G11C19/28 ,  H03K3/027 ,  H03K3/037 ,  H03K5/06 ,  H03K5/13 ,  H03K19/09 ,  H03K23/00

Abstract: 957,203. Transistor bi-stable circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 26, 1960 [Oct. 6, 1959], No. 32939/60. Heading H3T. [Also in Division G4] A transistor binary digit storage circuit for use in a shift register is formed substantially as shown in Fig. 3 or 5. The blocks A1 represent circuits of the type shown in Fig. 1 in which an output is produced only when both inputs are positive, blocks I are inverters similar to Fig. 1 but using only one input terminal and the delay is formed by two inverters connected in cascade. In Fig. 3, upon the occurrence of a shift pulse at 38 an output is produced at 39 corresponding to the input at 37 from the preceding stage and the output remains until the next pulse. Blocks 33 and 36 form a crosscoupled memory circuit which switches at the end of the shift pulse to correspond to the input at 37 and remains in this state until the termination of the next shift pulse. Fig. 5 operates in a similar manner except that the output at 79 is the inverse of that stored and to the output from 78. Several stages may be coupled together to form a shift register or ring counter (Fig. 4, not shown) in which case block 33 of one stage may be combined with block 31 of the next stage.

公开(公告)号：DE3854012T2

公开(公告)日：1996-02-15

申请号：DE3854012

申请日：1988-02-24

Applicant: IBM

Inventor： MALEY GERALD ADRIAN ,  WEITZEL STEPHEN DOUGLAS ,  MOSLEY JOSEPH MICHAEL

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/007

Abstract: A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one of the first and second interconnected signal paths.