公开(公告)号：WO02080267A3

公开(公告)日：2003-10-16

申请号：PCT/GB0201331

申请日：2002-03-20

Applicant: IBM ,  IBM UK

Inventor： LANZEROTTI LOUIS ,  MANN RANDY WILLIAM ,  MILES GLEN LESTER ,  MURPHY WILLIAM JOSEPH ,  VANSLETTE DANIEL SCOTT

IPC: H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/76855 ,  H01L21/76864

Abstract: A method of forming a liner (and resultant structure) in a contact for a semiconductor device includes depositing a first layer (201) of refractory metal, annealing the first layer, and sputter depositing a second layer (501) of refractory metal or a compound or an alloy thereof, over the first layer.

Abstract translation: 在半导体器件的接触中形成衬垫（和结构的结构）的方法包括沉积难熔金属的第一层（201），退火第一层，以及溅射沉积难熔金属或化合物的第二层（501） 或其合金，在第一层上。

公开(公告)号：ES2136148T3

公开(公告)日：1999-11-16

申请号：ES94115744

申请日：1994-10-06

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE ALFRED ,  D HEURLE FRANCOIS MAX ,  HARPER JAMES MCKELL EDWIN ,  MANN RANDY WILLIAM ,  MILES GLEN LESTER

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  C30B1/00

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.

公开(公告)号：AT183251T

公开(公告)日：1999-08-15

申请号：AT94115744

申请日：1994-10-06

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE ALFRED ,  D HEURLE FRANCOIS MAX ,  HARPER JAMES MCKELL EDWIN ,  MANN RANDY WILLIAM ,  MILES GLEN LESTER ,  RAKOWSKI DONALD WALTER DOUGLAS

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  C30B1/00

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.

公开(公告)号：SG160376A1

公开(公告)日：2010-04-29

申请号：SG2010016079

申请日：2007-07-31

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

Inventor： WENHE LIN ,  MANN RANDY WILLIAM ,  SHAFER PADRAIC C ,  BAIOCCO CHRISTOPHER VINCENT ,  ZHIJOING LUO ,  YANG HAINING S ,  XIANGDONG CHEN

Abstract: Some non-limiting example embodiments comprise a disposable spacer formation and removal process and a stress capping layer process. We provide a gate structure over a substrate. We form disposable spacers abutting the at least one gate sidewall. We form SID regions adjacent the disposable spacers. We remove the disposable spacers. We can form silicide regions over the SID and gate. In an aspect, we can deposit a stress inducing layer over the gate and surface portions of the substrate adjacent to the gate, wherein the stress inducing liner provides a stress to a portion of the substrate underlying the gate electrode. Fig. 7B

公开(公告)号：DE69420004T2

公开(公告)日：2000-03-30

申请号：DE69420004

申请日：1994-10-06

Applicant: IBM

Inventor： CABRAL CYRIL ,  CLEVENGER LAWRENCE ALFRED ,  D HEURLE FRANCOIS MAX ,  HARPER JAMES MCKELL EDWIN ,  MANN RANDY WILLIAM ,  MILES GLEN LESTER ,  RAKOWSKI DONALD WALTER DOUGLAS

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  C30B1/00

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.

公开(公告)号：BR9404247A

公开(公告)日：1995-06-20

申请号：BR9404247

申请日：1994-10-26

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE ALFRED ,  D'HERLE FRANCOIS MAX ,  HARPER JAMES MCKELL EDWING ,  MANN RANDY WILLIAM ,  MILES GLEN LESTER ,  RAKOWSKI DONALD WALTER DOUGLAS

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L23/36

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.

公开(公告)号：SG141310A1

公开(公告)日：2008-04-28

申请号：SG2007055494

申请日：2007-07-31

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

Inventor： WENHE LIN ,  MANN RANDY WILLIAM ,  SHAFER PADRAIC C ,  BAIOCCO CHRISTOPHER VINCENT ,  ZHIJOING LUO ,  YANG HAINING S ,  XIANGDONG CHEN

Abstract: FET STRUCTURE USING DISPOSABLE SPACER AND STRESS INDUCING LAYER Some non-limiting example embodiments comprise a disposable spacer formation and removal process and a stress capping layer process. We provide a gate structure over a substrate. We form disposable spacers abutting the at least one gate sidewall. We form S/D regions adjacent the disposable spacers. We remove the disposable spacers. We can form silicide regions over the S/D and gate. In an aspect, we can deposit a stress inducing layer over the gate and surface portions of the substrate adjacent to the gate, wherein the stress inducing liner provides a stress to a portion of the substrate underlying the gate electrode.

公开(公告)号：DE69420004D1

公开(公告)日：1999-09-16

申请号：DE69420004

申请日：1994-10-06

Applicant: IBM

Inventor： CABRAL CYRIL ,  CLEVENGER LAWRENCE ALFRED ,  D HEURLE FRANCOIS MAX ,  HARPER JAMES MCKELL EDWIN ,  MANN RANDY WILLIAM ,  MILES GLEN LESTER ,  RAKOWSKI DONALD WALTER DOUGLAS

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  C30B1/00

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.