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    High-word facility for extending the number of general purpose register available to instruction
    1.
    发明专利
    High-word facility for extending the number of general purpose register available to instruction 有权
    提高可用于指导的一般用途注册号码的高字节设施

    公开(公告)号：JP2013242918A

    公开(公告)日：2013-12-05

    申请号：JP2013162972

    申请日：2013-08-06

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： DANIEL F GLINER ,  MARCEL MITRAN ,  TIMOTHY J SIEGEL

    IPC: G06F9/34

    CPC classification number: G06F9/3012 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/342

    Abstract: PROBLEM TO BE SOLVED: To provide new instruction functionality consistent with an existing architecture.SOLUTION: Dependency on architecture resources such as general registers is relieved, and functionality and performance of software versions employing the new instruction are improved. A computer employs a plurality of general purpose registers. Each general purpose register comprises a high order portion and a low order portion. Programs such as an operating system and applications operating in a large-capacity addressing mode, access the full general purpose registers, however programs such as applications operating in small-capacity addressing mode, only have access to a portion at a time. Instruction Opcodes, in small-capacity addressing mode, may determine which portion is accessed.

    Abstract translation: 要解决的问题：提供与现有架构一致的新指令功能。解决方案：解决了对通用寄存器等架构资源的依赖性，并提高了采用新指令的软件版本的功能和性能。 计算机采用多个通用寄存器。 每个通用寄存器包括高阶部分和低阶部分。 诸如操作系统和以大容量寻址模式运行的应用程序之类的程序访问完整的通用寄存器，然而诸如以小容量寻址模式运行的应用程序的程序只能一次访问一部分。 指令操作码在小容量寻址模式下，可以确定访问哪个部分。

    Command for performing operation to two operands and storing original values of operands
    2.
    发明专利
    Command for performing operation to two operands and storing original values of operands 有权
    执行操作的两项操作和存储操作原始值的命令

    公开(公告)号：JP2012009021A

    公开(公告)日：2012-01-12

    申请号：JP2011133183

    申请日：2011-06-15

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： DANIEL F GLINER ,  MARCEL MITRAN ,  TIMOTHY J SIEGEL

    IPC: G06F9/34

    CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30167

    Abstract: PROBLEM TO BE SOLVED: To provide a new command function which reduces dependency on an architecture resource, such as a general-purpose register, improves a function and performance of a software version using a new command, and is consistent with existing architecture.SOLUTION: When an arithmetic/logical command having an interlocked memory operand is executed, a second operand is acquired from a position in a memory, and a temporary copy of the second operand is stored. On the basis of the second operand and a third operand, arithmetic operation or logical operation is performed, a result is stored to a memory position of the second operand, and then the temporary copy is stored to a first register.

    Abstract translation: 要解决的问题：为了提供减少对诸如通用寄存器的架构资源的依赖性的新的命令功能，使用新的命令来改进软件版本的功能和性能，并且与现有架构一致 。 解决方案：当执行具有互锁存储器操作数的算术/逻辑命令时，从存储器中的位置获取第二操作数，并存储第二操作数的临时副本。 基于第二操作数和第三操作数，执行算术运算或逻辑运算，将结果存储到第二操作数的存储位置，然后将临时副本存储到第一寄存器。 版权所有（C）2012，JPO＆INPIT

    instrução de fim de transação condicional
    4.
    发明专利
    instrução de fim de transação condicional 未知

    公开(公告)号：BR112016021216A2

    公开(公告)日：2021-06-08

    申请号：BR112016021216

    申请日：2015-02-23

    Applicant: IBM

    Inventor： CHRISTIAN JACOBI ,  DAN GREINER ,  DONALD WILLIAM SCHMIDT ,  MARCEL MITRAN ,  TIMOTHY SLEGEL

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46

    Abstract: instrução de fim de transção condicional uma instrução de fim de transação condicional é fornecida que permite que um programa em execução em um modo de execução transacional não restrito inspecione um local de armazenamento que é modificado por qualquer outra unidade de processamento central ou o subsistema de entrada / saída. com base nos dados inspecionados, a execução transacional pode ser encerrada ou interrompida, ou a decisão de encerrar / interromper pode ser adiada, por exemplo, até que um evento predefinido ocorra. por exemplo, quando a instrução é executada, o processador está num modo de execução da transação não restrita, e a profundidade de sobreposição de transação é uma no início da instrução, um segundo operando da instrução é inspecionado, e com base nos dados inspecionados, a execução da transação pode ser terminada ou interrompida, ou a decisão de terminar / abortar pode ser adiada, por exemplo, até que um evento predefinido ocorra, tal como o valor do segundo operando torna-se um valor pré-especificado, ou um intervalo de tempo for excedido.

    Conditional Instruction End Operation
    5.
    发明专利
    Conditional Instruction End Operation 未知

    公开(公告)号：GB2542278B

    公开(公告)日：2020-08-05

    申请号：GB201616977

    申请日：2015-03-11

    Applicant: IBM

    Inventor： DAN GREINER ,  TIMOTHY SLEGEL ,  CHRISTIAN JACOBI ,  DONALD WILLIAM SCHMIDT ,  MARCEL MITRAN

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed. The obtaining the operand, the determining whether the operand has the predetermined relationship, the based on determining that the operand does not have the predetermined relationship with respect to the value, repeating the obtaining and the determining, and the based on determining that the operand has the predetermined relationship with respect to the value, completing execution of the instruction are performed as part of a single instruction having one operation code.

    Conditional instruction end machine instruction
    10.
    发明专利
    Conditional instruction end machine instruction 未知

    公开(公告)号：GB2542278A

    公开(公告)日：2017-03-15

    申请号：GB201616977

    申请日：2015-03-11

    Applicant: IBM

    Inventor： DAN GREINER ,  TIMOTHY SLEGEL ,  CHRISTIAN JACOBI ,  DONALD WILLIAM SCHMIDT ,  MARCEL MITRAN

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed. The obtaining the operand, the determining whether the operand has the predetermined relationship, the based on determining that the operand does not have the predetermined relationship with respect to the value, repeating the obtaining and the determining, and the based on determining that the operand has the predetermined relationship with respect to the value, completing execution of the instruction are performed as part of a single instruction having one operation code.

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