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公开(公告)号：GB2593852B
公开(公告)日：2022-03-09
申请号：GB202111895
申请日：2020-01-16
Applicant: IBM
Inventor： CHRISTOPH RAISCH , MARCO KRAEMER , FRANK LEHNERT , MATTHIAS KLEIN , JONATHAN BRADBURY , CHRISTIAN JACOBI , BRENTON BELMAR , PETER DRIEVER
Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.
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公开(公告)号：IL284763D0
公开(公告)日：2021-08-31
申请号：IL28476321
申请日：2021-07-11
Applicant: IBM , GIRISH GOPALA KURUP , MATTHIAS KLEIN , ANTHONY T SOFIA , JONATHAN D BRADBURY , ASHUTOSH MISRA , CHRISTIAN JACOBI , DEEPANKAR BHATTACHARJEE
Inventor： GIRISH GOPALA KURUP , MATTHIAS KLEIN , ANTHONY T SOFIA , JONATHAN D BRADBURY , ASHUTOSH MISRA , CHRISTIAN JACOBI , DEEPANKAR BHATTACHARJEE
Abstract: An aspect includes a system architecture that includes a processing unit, an accelerator, a main source buffer, a main target buffer, and a memory block. The main source buffer stores a first part of a source symbol received from an external source. The main target buffer stores an output symbol received from the accelerator. The memory block includes an overflow source buffer that stores the first part of the source symbol received from the main source buffer. The accelerator fetches the first part of the source symbol stored in the overflow source buffer and a second part of the source symbol stored in the main source buffer, and converts the first and second parts of the source symbol together into the output symbol. The second part of the source symbol includes a part of the source symbol not included in the first part of the source symbol.
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公开(公告)号：BR112014022726A2
公开(公告)日：2021-07-27
申请号：BR112014022726
申请日：2012-11-15
Applicant: IBM
Inventor： CHRISTIAN JACOBI , ERIC MARK SCHWARZ , JONATHAN DAVID BRADBURY , MICHAEL KARL GSCHWIND , TIMOTHY SLEGEL
IPC: G11C11/00
Abstract: instrução para computar a distância para uma fronteira de memória específica. é fornecida uma instrução de contagem de carga para limite de bloco que fornece uma distância a partir de um endereço especificado de memória para um limite especificado de memória. o limite de memória é um limite que não deve ser cruzado durante o carregamento de dados. o limite pode ser especificado de várias maneiras, incluindo, mas não limitado a, um valor variável no texto de instrução, um valor de texto de instrução fixo codificado no código de operação ou um limite baseado em registro; ou pode ser dinamicamente determinado.
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公开(公告)号：IL282055D0
公开(公告)日：2021-05-31
申请号：IL28205521
申请日：2021-04-04
Applicant: IBM , BRUCE C GIAMEI , MARTIN RECKTENWALD , DONALD W SCHMIDT , TIMOTHY SLEGEL , ADITYA N PURANIK , MARK S FARRELL , CHRISTIAN JACOBI , JONATHAN D BRADBURY , CHRISTIAN ZOELLIN
Inventor： BRUCE C GIAMEI , MARTIN RECKTENWALD , DONALD W SCHMIDT , TIMOTHY SLEGEL , ADITYA N PURANIK , MARK S FARRELL , CHRISTIAN JACOBI , JONATHAN D BRADBURY , CHRISTIAN ZOELLIN
IPC: G06F9/30 , G06F16/242
Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.
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5.发明专利
公开(公告)号：PT2769305T
公开(公告)日：2018-07-27
申请号：PT12871072
申请日：2012-11-15
Applicant: IBM
Inventor： JONATHAN DAVID BRADBURY , MICHAEL KARL GSCHWIND , TIMOTHY SLEGEL , ERIC MARK SCHWARZ , CHRISTIAN JACOBI
IPC: G06F9/30
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Patent Agency Ranking
公开(公告)号：MX2017007060A
公开(公告)日：2017-11-08
申请号：MX2017007060
申请日：2015-10-30
Applicant: IBM
Inventor： CHRISTIAN JACOBI , JONATHAN DAVID BRADBURY , TIMOTHY SLEGEL , MICHAEL KARL GSCHWIND
Abstract: Un método para acceder a los datos en una memoria acoplada a un procesador, que comprende: recibir una instrucción de la referencia de la memoria para acceder a los datos de un primer tamaño en una dirección en la memoria; determinar un tamaño de la alineación de la dirección en la memoria; y acceder a los datos del primer tamaño en uno o más grupos de datos accediendo a cada bloque de grupo de datos de manera concurrente. Los grupos de datos tienen tamaños que son múltiplos del tamaño de la alineación.
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公开(公告)号：BR112014031435A2
公开(公告)日：2017-06-27
申请号：BR112014031435
申请日：2013-05-03
Applicant: IBM
Inventor： CHRISTIAN JACOBI , DAN GREINER , TIMOTHY SLEGEL
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公开(公告)号：BR112014031350A2
公开(公告)日：2017-06-27
申请号：BR112014031350
申请日：2012-11-26
Applicant: IBM
Inventor： CHRISTIAN JACOBI , DAN GREINER , MARCEL MITRAN , TIMOTHY SLEGEL
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公开(公告)号：GB2632957A
公开(公告)日：2025-02-26
申请号：GB202416053
申请日：2023-01-17
Applicant: IBM
Inventor： ADAM COLLURA , MICHAEL ROMAIN , WILLIAM HUOTT , PAWEL OWCZARCZYK , CHRISTIAN JACOBI , ANTHONY SAPORITO , CHUNG-LUNG SHUM , ALPER BUYUKTOSUNOGLU , TOBIAS WEBEL , MICHAEL CADIGAN JR , PAUL LOGSDON , SEAN CAREY , KARL ANDERSON , MARK CICHANOWSKI , STEFAN PAYER
Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. The method includes detecting a region, such as an individual processor, of a processor chip exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life. The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltage spikes back to within some pre-specified range. The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.
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公开(公告)号：IL284466D0
公开(公告)日：2021-08-31
申请号：IL28446621
申请日：2021-06-29
Applicant: IBM , BRUCE C GIAMEI , ANTHONY T SOFIA , MATTHIAS KLEIN , SIMON WEISHAUPT , MARK S FARRELL , TIMOTHY SLEGEL , ASHUTOSH MISHRA , CHRISTIAN JACOBI
Inventor： BRUCE C GIAMEI , ANTHONY T SOFIA , MATTHIAS KLEIN , SIMON WEISHAUPT , MARK S FARRELL , TIMOTHY SLEGEL , ASHUTOSH MISHRA , CHRISTIAN JACOBI
Abstract: An instruction to perform a function of a plurality of functions is obtained. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes performing the function specified by the instruction. The performing includes, based on the function being a compression function or a decompression function, transforming state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data accessing. During performing the function, history relating to the function is accessed. The history is to be used in transforming the state of input data between the uncompressed form and the compressed form.
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