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    Digital data storage system
    1.
    发明授权
    Digital data storage system 失效
    数字存储系统

    公开(公告)号：US3771142A

    公开(公告)日：1973-11-06

    申请号：US3771142D

    申请日：1972-05-01

    Applicant: IBM

    Inventor： MINSHULL J ,  MURPHY A

    IPC: G06F7/78 ,  G11C15/04 ,  G11C15/00

    CPC classification number: G06F7/78 ,  G11C15/04

    Abstract: Storage space in an associative store is freely allocated between a plurality of I/O devices. Initially, each register of the store contains a number belonging to a cyclic number sequence. A number is erased when data is entered into a register and the highest (taking wrap around into account) unused number is placed in a register when data is removed. Data associated with a given device is tagged with the device address and can be stored in first-in first-out or last-in first-out modes. In an alternative embodiment when sufficient data has been accumulated from a device, it is labelled as a data block. Data blocks can be transferred from the store in priority order determined either by the associated device and/or the content of the block.

    Input/output channel
    2.
    发明授权
    Input/output channel 失效
    输入/输出通道

    公开(公告)号：US3729716A

    公开(公告)日：1973-04-24

    申请号：US3729716D

    申请日：1971-02-12

    Applicant: IBM

    Inventor： ARULPRAGASAM J ,  MINSHULL J ,  MURPHY A

    IPC: G06F13/12 ,  G11C15/04 ,  G06F3/00 ,  G06F15/16

    CPC classification number: G11C15/04 ,  G06F13/122

    Abstract: A multiplex input/output (I/O) channel in which channel functions are carried out by associative stores. Three associative stores are used, a control store, an address store and a data store. The data store acts as a data buffer store and also handles most of the interchange of control signals between the channel and the I/O control units. Tag-in I/O signals are used directly as keys in table look-up on interface response tables and initiate the appropriate response from the channel. The address store assemblies the main store address and is also responsible for some of the tag-out I/O signals. Subchannels are allotted only when they are needed. There are a limited number of subchannel areas and these are marked when they are allotted to control units. An extra marker identifies the subchannel currently in use. Any control unit can be allotted to any subchannel.

    Abstract translation: 通过关联存储进行通道功能的复用输入/输出（I / O）通道。 使用三个关联商店，控制商店，地址存储和数据存储。 数据存储器充当数据缓冲存储器，并且还处理通道和I / O控制单元之间的大多数控制信号的交换。 标签输入/输出信号直接用作接口响应表的查询表中的键，并从通道启动适当的响应。 地址存储器组装主存储地址，并且还负责一些标记输出I / O信号。 仅在需要时才分配子通道。 子通道区域数量有限，当它们分配给控制单元时，这些区域被标记。 一个额外的标记标识当前正在使用的子通道。 任何控制单元都可以分配给任何子通道。

    DATA PROCESSING SYSTEM
    3.
    发明专利
    DATA PROCESSING SYSTEM 未知

    公开(公告)号：CA935940A

    公开(公告)日：1973-10-23

    申请号：CA66919

    申请日：1969-11-07

    Applicant: IBM

    Inventor： MINSHULL J ,  LLEWELYN R

    IPC: G06F9/26 ,  G06F9/22 ,  G06F9/32 ,  G06F9/34 ,  G06F9/38 ,  G06F12/08 ,  G11C15/04

    Abstract: 1,234,484. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 12 Nov., 1968, No. 53517/68. Heading G4A. An electronic data processing system comprises a control store controlling (a) execution of functions by table-look-up procedures in an associative working store and (b) execution by table-look-up procedures in an associative address store of functions on address data to be used in addressing a non-associative data store in the system, the arrangement being such that simultaneous execution can take place in the working and address stores. The control store, which is associative, supplies tags for interrogating the associative working and address stores and an associative local store (which comprises registers). A 4-byte ADD instruction is read, two bytes at a time, from the data store addressed from an instruction counter in the address store, the op code being interpreted in the working store to select the microprogramme used to access the operands. The instruction specifies the register holding the first operand, and a displacement and two further registers, the displacement and contents of the two further registers being added serially by byte using table-look-up in the working store to obtain the address in the data store of the second operand. This address, supplied serially by byte as formed, is inserted into the right-most byte position of the input-output register of the address store and shifted along utilizing tablelook-up in a shift table in the address store, until the whole address is present when it is used for addressing the data store. Shift.-Each word in the shift table has a single 1, every other bit being a " don't care," and successive words have the 1 in positions 1, 1; 2, 1; 3, 1; 4, 1; 1, 2; 2,2; 3, 2; 4,2; 1, 3 &c., where the first digit is the byte position and the second is the bit position, numbered from the right. As each byte arrives in the input-output register, the register is used to interrogate all the words in the shift table and the word immediately following each word giving a match is read out, these words being read out simultaneously, corresponding bits being ORed, the result going into the input-output register. Invalid address check.-The associative address store may have a table for detecting any 1 bit in the highest order byte or lowest order bit of an address, each word in the table having a single 1 bit in a different position for interrogating, the other bits interrogated being " don't cares," a match causing read out of an error 1 bit. Alternatively, such error 1 bits may be included in the shift table for the same purpose. Specifications Nos. 1,127,270, 1,186,703, 1,218,406 are referred to, the first two for suitable associative stores and the last as being a system of which the present invention is a modification.

    ELECTROCHROMIC DISPLAY DEVICE
    6.
    发明专利
    ELECTROCHROMIC DISPLAY DEVICE 未知

    公开(公告)号：CA1054738A

    公开(公告)日：1979-05-15

    申请号：CA262063

    申请日：1976-09-27

    Applicant: IBM

    Inventor： HALLETT M ,  BARCLAY D ,  MINSHULL J ,  BIRD C ,  KIRKMAN D ,  OWEN C

    IPC: G04G9/00 ,  C25D11/00 ,  G02F1/163 ,  G09F9/30 ,  G09G3/16 ,  G09G3/19 ,  G09G3/38 ,  G06K15/18 ,  G09F9/00

    Abstract: In addition to the usual two electrodes of an electro-chromic cell at which balanced reactions take place, at least one further electrode is provided. Operation of the display is preceded by applying potential to the two electrodes so that one of them carries a coloured precipitate. Then, a relatively small potential across the a coloured electrode and a selected further electrode transfers the colour to the further electrode. Ohmic connection between the coloured electrode and the further electrode does not cause the colour to dissipate. One application is to a 7 - element digit display and a matrix display comprises columns of electrodes each headed by said two electrodes (called dump and transfer electrodes respectively) and including a plurality of further electrodes. Means for addressing and sensing such a display are described.

    10.
    发明专利
    未知

    公开(公告)号：SE353408B

    公开(公告)日：1973-01-29

    申请号：SE568870

    申请日：1970-04-24

    Applicant: IBM

    Inventor： FLINDERS M ,  GARDNER P ,  HALLETT J ,  JONES J ,  MINSHULL J ,  TAYLOR K

    IPC: G06F12/16 ,  G06F11/16 ,  G11C15/04 ,  G06F11/00

    Abstract: 1,265,013. Electric digital data storage: computers. INTERNATIONAL BUSINESS MACHINES CORP. 24 April, 1969, No. 20902/69. Headings G4A and G4C. Error detecting circuitry checks data transfer between two registers to provide an error signal only in the absence of a bit of one value in any order of the second register when the same order of the first register contains a bit of the one value. In Fig. 1 two associative stores 1, 2 storing the same information have a selector trigger 4 (to indicate match) for each word location 3, and each have two input/output registers 12, 13 for store 1 and 15, 16 for store 2. Register 13 can also feed and be fed by a bus 23, register 16 can be fed by bus 23, register 12 can be fed by a bus 24, and register 15 can feed and be fed by bus 24, via drivers 26, 30 and receivers 25, 26, 28, 29. One or more further pairs of associative stores may be connected to the buses 23, 24 as may non-associative stores, and the buses communicate with each other via a buffer which may be in the main memory of a computer system using the invention or may be a single separate register. Error features.-During simultaneous associative search in stores 1 and 2 using the same search argument from registers 12, 15 or 13, 16, comparators 6 produce an error signal if different selector triggers 4 are set by the two stores. After read, comparators 18 produce an error signal if input/output registers 12 and 15, or 13 and 16, have unequal contents (only one pair of registers is loaded from the store). Following this, to transfer out the read information and prepare for the next associative search, registers 13, 15 are gated (by actuating drivers 26, 30) to buses 23, 24 respectively, the buses being gated (by actuating receivers 27, 28) to registers 16, 12 almost immediately afterwards. An error signal is now produced unless there is a 1 in register 12 for each 1 in register 15 and a 1 in register 16 for each 1 in register 13 (this form of check being used since other stores may be using the buses simultaneously so a simple equal/unequal check cannot be used). Parity circuits 31, 33 connected in series, generate the parity of the data being supplied to registers 12, 16 from the buses 24, 23 (see above) and this parity is compared (not shown) with parity generated for the data on the buses by two parity circuits (not shown) connected to the respective buses and in series with each other, an error signal being produced on inequality. The buses 23, 24 are now gated (by actuating receivers 25, 29) to the registers 13, 15. An error signal is produced if registers 12 and 15, or 13 and 16, are now unequal as determined by comparators 18. After a write operation, all the receivers are actuated to load registers 12, 13, 15, 16 from the buses for the next associative search, parity checking, and an inequality check by 18, being done as above. After associative interrogation, an extra check on the drivers 26, 30 is done by inhibiting all drivers (of all pairs of stores linked to the buses) and generating the parity of the data on the buses, an error signal being produced if it is non-zero. Detection of any error causes retry (repetitive) of the storage cycle giving the error. If this is unsuccessful and the error can be attributed to data errors, an incorrect word is replaced by its duplicate from the other store 1 or 2 followed by retry. If still unsuccessful, or if the error cannot be attributed to data errors, lines 42, 43 are de-energized to isolate the pair of stores from the buses. If the error signal came from mismatched selector triggers 4, the selector triggers are reset (their states having been saved in a diagnostic column of each store 1, 2), then set in turn by a " next " operation which causes a 1 to shift down each column of triggers 4. If the is do not arrive at the bottoms of the columns simultaneously (even after retires) the the stores are isolated from the buses. If they do arrive simultaneously a read operation is performed and if comparators 18 (which should be comparing zeroes) detect inequality, the selector triggers 4 are not resetting properly, so the stores are isolated from the buses. If this does not happen, the " next " operation is good, and is used repeatedly to read out successive bits of the diagnostic columns for comparison at 18, inequality causing the rest of the words corresponding to the unequal diagnostic column bits to be read out for parity checks (by means not shown). If both words have correct parity, the stores are isolated, but if only one is correct, the incorrect word is replaced by the correct one via the two buses. Fig. 6 (not shown) shows two stages of a parity circuit having a stage for each bit position of a word whose parity is to be generated. A typical stage comprises a transistor tree controlled by a parity input in true and complement form from the preceding stage, and by the corresponding bit of the word, to produce a parity output in true and complement form to the next stage. The circuit can also be used for checking parity. Fig. 7 (not shown) shows one stage of a comparator, having outputs indicating (A and not B), (B and not A) respectively, where A, B are the bits being compared. Both outputs are sensed for the inequality comparison and only one for the ones comparison above.

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